vhdl 中文意思是什麼
vhdl
解釋
極高密度脂蛋白-
( 3 ) the dissertation designs the hardware diagrams of corelation matrix module and spectrum peak finding module. accroding to the hardware diagrams, the dissertation codes by vhdl and do function simulation and timing simulation
（ 4 ）本文對music演算法的各模塊進行了互連調試工作。當採用了altera公司cyclone系列的fpga實現music演算法時，單次運算時間在20us以內。 -
The design of digital cymometer based on vhdl
語言的數字頻率計設計 -
Thus, the vhdl is carried to make a design for the forenamed algorithms, and the design is validated by simulation
因此，本文用vhdl語言實現了ca邊緣檢測演算法模型的基本內核設計，並通過時序模擬，進行了演算法的硬體設計與效果驗證。 -
This paper introduces the principle of the frequency division and presents the circuit design of the decimal frequency divider based on fpga. the vhdl language is used for the programming
摘要介紹了一種基於fpga的小數分頻器的分頻原理及電路設計，並用vhdl進行編程實現，並對這種小數分頻器的抖動進行分析和計算。 -
Vhdl - based data monitor and interception system of i2c bus
總線數據監視採集系統 -
Multi - body systems ' modeling and simulation method for mechatronics design based on vhdl - ams
的多剛體系統建模與模擬方法 -
Thi s dissertation first describes syntax, semanteme and method of modeling hardware of veri1og hdl and vhdl in detai1 so that strong abi1 ity of designing and simu1ating waveform is represented in hardware circuits
本文首先對兩種硬體描述語言veriloghdl和vhdl在語義、語法及硬體建模方法進行了詳細的描述，說明它們在硬體電路波形表示方面有較強的設計與模擬能力。 -
Covers many related topics : eda tools, vhdl, verilog ; fabrication ; fpgas, asics, microprocessors, semiconductors, cmos
-提供it類產品資訊，評測，新聞，導購信息。擁有多商家體系的電子商務模式 -
Covers many related topics : eda tools, vhdl, verilog ; fabrication ; fpgas, asics, microprocessors, semiconductors, cmos. usenet comp. arch -
-提供企業級類比式與數位式kvm切換器序列操作臺控制遠端存取以及集中伺服器管理解決方案領先全球的供應廠商。 -
Behavioural languages - vhdl language reference manual
行為語言. vhdl語言參考手冊 -
However, the longer length of c / a code, the more hardware resource and power it cost. this dissertation commits research on algorithm of c / a code acquisition in satellite navigation position system, and compares the acquisition means of digital differential matched filter ( ddmf ) with traditional means, and also achieves ddmf with the vhdl language and fpga platform
擴頻碼的周期的加長會給衛星導航定位系統帶來許多相應的好處，但問題也就隨著之而來了，擴頻碼的周期越長，同步捕獲所需得的時間就越長，而且若用傳統的并行捕獲方法，將極大的耗費硬體資源，而且系統功耗會隨之增大。 -
At last the algorithm of ddmf is achieved by the investigation tool of altera company ? quartus ii and the vhdl language, and its ip core is also achieved which is used not only in the satellite navigation position system, but also in the long pn code dsss system. ddmf investigated in the dissertation gives a good way to design the rapid pn code acquisition in the beidou project, and the technology has the definite theory and practice significance
此外還應用altera公司的最新的fpga開發工具quartusiiv5 . 1 ，採用了國際標準的硬體描述語言? vhdl語言，對數字差動匹配濾波器和傳統匹配濾波器演算法予以實現，開發了該演算法的軟ip核，可以對所應用的擴頻碼長度， a / d采樣后的數據量化階數，所用擴頻碼等可進行隨意改寫。 -
The key to the fft algorithm is the design of butterfly computation and that of the address logic. the whole schema is designed in the top - down design flow and described in the vhsic hardware description language ( vhdl ), basing on these, we do our research on reconfigurable technology. the result indicates that the data processing ability of reconfigurable system improved greatly
結果表明，可重構系統在數據處理能力方面比以往的系統有了很大的提高，本設計實現的fft重構處理器可工作於60mhz下，完成一個16點fft需要132個主時鐘周期，完成32點fft需要324個主時鐘周期，而且具有一定可重構性，可以方便地將其運算點數進行擴展，或將其他的圖像處理演算法在實時處理系統中實現。 -
The study of denotational semantics of vhdl
西方語言哲學研究的現狀與前景 -
Adopting the method of top - down, the virtual memory is divided into memory mange related unit ( segment unit and page unit ) and protection mode related unit ( protection test unit, debug test unit and exception detect unit ). data buses and control bused are designed separately for all of the units. vhdl codes are written and simulated
Amex86的虛擬存儲器採用自頂向下的設計方法，把虛擬存儲器劃分為地址管理相關單元（又包括分段單元和分頁單元） 、保護模式相關單元（又包括保護測試單元、調試異常單元利異常檢測單元等） ，分別確立其數據通路和控制通路，完成了vhdl的編碼和模擬工作，通過測試程序模擬驗證了其功能的正確性並測定了基本性能。 -
It implements filter groups design, wide range linear automatic gain control design, and the programmed logic device design based on vhdl, and discuss their application in initial radar system in details
其中包括分段濾波器的設計技術，寬線性自動增益控制agc電路的設計技術，以及基於vhdl語言的可編程邏輯器件的設計技術，並對其在數據採集系統中的應用作了詳細的討論。 -
Above all, [ 12 : 8 ] harming error correction theory is mentioned in this paper. the edac circuit designed by vhdl can works normally at different frequency of the cpu clock such as 66mhz 50mhz 40mhz 33mhz. the edac function of the circuit can also be disabled by software tool. meanwhile, some basic devices such as and logic, or logic, not logic and some small scale integrated circuits are also integrated in the fpga
本論文闡述了12 ， 8漢明碼糾錯設計過程，採用vhdl語言實現糾錯編碼器（ edac ） ，本設計能夠適應cpu時鐘信號clk2的不同頻率，如66mhz 、 50mhz 、 40mhz 、 33mhz ，並且能夠通過軟體的控制使fpga的糾錯編碼功能關閉。 -
After that, the hardware circuit, especially some of the key parts, is investigated in detail. the following processes are also investigated in detail : empoldering the four fold - frequency subdivision 、 direction - judgment 、 counting and flip - latch of the data with vhdl ( very high speed integrated circuit hardware description language ) ; empoldering the serial interface and the data collection software in pc with borland c + + builder
接下來詳細介紹了使用vhdl語言開發fpga晶元的細分、辨向、計數、鎖存以及串列傳輸處理等全部功能;用borlandc + + builder開發了pc機上的串列介面、數據採集軟體;設計並製作了fpga晶元及其外圍電路的電路板。 -
Finally, vhdl is used to descript the algorithm upwards. multimedia information encryption / decryption system is designed then
最後，本文使用vhdl對上述演算法進行描述，設計了以fpga為核心的多媒體信息加密系統。 -
Inquiry about majorization of vhdl language in circuit design
語言在電路設計中的優化探討
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