介面寄存器 的英文怎麼說

中文拼音 [jièmiànjìcúnqì]
介面寄存器 英文
interface register
  • 面 : Ⅰ名詞1 （頭的前部; 臉） face 2 （物體的表面） surface; top 3 （外露的一層或正面） outside; the ri...
  • 存 : 動詞1 （存在; 生存） exist; live; survive 2 （儲存; 保存） store; keep 3 （蓄積; 聚集） accumulat...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 介面 : joggle; nozzle; mouthpiece; [計算機] interface
  1. Let s look at each of these in detail

    下面詳細介紹這些段寄存器。
  2. This digital pattern generator composes of eight parts : interface circuit unit, dual - port sram unit, dsp unit, dac unit, expose / mark signal detection control unit, mark signal diction unit and final expose shape registers unit

    本論文中的新型圖形發生器由介面電路、雙埠存儲電路、數字信號處理電路、數模轉換電路、曝光標記檢測控制電路、標記檢測電路、最終曝光數據寄存器單元和束閘控制電路構成。
  3. The configuration that uses ieee - 13 94 to control a vxi system is introduced. chapter 2 describes the resource manager application of message - based device 13 94 - vxi controller and the mechanism of register - based device arbitrary waveform generator ( awg ). the key technology of interface circuit and direct digital synthesis in awg module is discussed explicitly

    本文先對vxi總線技術進行了概略的介紹，在此基礎上，對一具體的vxi寄存器基任意波形發生器模塊進行展開，介紹了任意波形發生器模塊與vxi機箱背板總線通訊的介面電路部分及波形發生機理的核心部分的直接數字合成技術。
  4. The bus is programable. at this rate the user can program the mcu firmware to configure the correlative registers before using the bus. the user can also change the bus channel in the gpmb when the data of different type is to be transfered. in conclusion, gpmb module provides the communication channel between usb2. 0 ip core and peripheral

    它提供32位可編程介面，用戶可以通過usb2 . 0ip核中的mcu固件對內部相關寄存器進行配置來使用這32位總線，並可以在內部的多總線通道中切換，以達成usb2 . 0ip核對外圍介面的控制及數據傳輸，進而完成設備通過usb2 . 0介面ip核與主機通信的功能。
  5. H. 323 is the standard about multimedia communication released by itu - t. tm1300 including a very powerful, general - purpose vliw processor core ( the dspcpu ) that coordinates all on - chip activities is a media processor for high - performance multimedia applications that deal with high - quality video and audio. the dspcpu implements a 32 - bit linear address space and 128, fully general - purpose 32 - bit registers

    H . 323是itu ? t推出的用於ip分組網路的多媒體通信終端協議， trimediatm1300處理器晶元是philips公司推出的一種基於多媒體應用的具有vliw指令，含有128個通用寄存器， 32位的高性能處理器，它能夠通過編程實現通信協議，完成高質量的音頻、視頻處理和網路介面。
  6. In this paper, the methodology and implementation with hdl of design based reconfigurable architecture are discussed in detail, which includes the implementations of algorithms circuit, register file with controllable node, decoder, interface and main controller. from the introduction of design process of every module circuit, we can see easily some general feature of vlsi design with hdl

    在此基礎上詳細討論了基於可重組體系結構的密碼晶元設計方法和各電路實現的結構圖，包括演算法電路、可控節點寄存器堆、譯碼電路、介面電路和主控模塊電路等。通過對各個模塊設計過程的介紹，闡明了使用hdl語言設計超大規模集成電路的一般特點。
  7. A typical calculator chip from rcl semiconductor inc, c9821, is referenced and developed. the chip of the calculator consists of several function units such as rc oscillator, power management module, microprogrammed control unit ( mcu ), register group, lcd driver and keyboard interface

    在硬體方面，在完成計算器的功能模塊劃分的基礎上，對包括rc振蕩器、電源模塊、 lcd顯示驅動模塊、鍵盤介面、寄存器組、微程序控制器在內的各個功能模塊的系統結構和電路原理進行了分析，掌握了它們的設計方法。
  8. Making use of the powerful capabilities of the pci chip, high - speed data of the dsp platform are transferred both ways at dma mode, and low speed data such as initialization and configuration information are transferred at direct slave mode. this paper shows in detail the workings of pci9054, the configuration of its control register, and the writing of platform driver with api functions provided by the manufacturer

    利用pci介面晶元的強大功能，本文提出了採用dma模式雙向傳輸dsp平臺的高速數據，採用從模式傳輸初始化信息及配置信息等低速數據，並詳細介紹了pci9054的工作方式，控制寄存器的配置以及調用廠商提供的api函數編寫平臺驅動程序。
  9. 3. realize the interface between pci9054 and the pci bus, including the bus arbitration, read and write of the registers, the configuration of the eeprom, the dma transfer, interrupt response and so on

    3 .實現pci9054與計算機pci總線的介面，包括總線仲裁，寄存器讀寫操作， eeprom的配置和下載， dma傳輸，中斷響應等功能。
  10. The integrated register based vxibus interface is designed by using the advanced cpld technology. this method simplifies the interface circuit design and improves its reliability. 2

    利用cpld技術自行設計了vxi總線寄存器基集成化介面電路和數據採集控制電路，從而簡化了電路的設計，提高了可靠性。
  11. The serial a / d transformation and the channel isolation technology are adopted. eight - channel parallel data acquisition and test data time - sharing storage are realized. verilog hdl ( hardware description language ) is adopted to design the vxi register - based interface circuit and control circuit of each channel

    以fpga （ fieldprogrammablegatearray ）為控制核心，採用串列a / d變換器和通道隔離技術，實現了8通道并行採集和測試數據分時存儲功能，利用veriloghdl （ hardwaredescriptionlanguage ）設計vxi寄存器基介面電路及各通道的控制電路。
  12. Finally, the sci module is integrated inside the chip, and reduce the cost of system. besides, there are many programmable registers inside the sci, so it possesses better compatible abilities, it could not only support smart card based on iso7816, but also support smart card base on gsm, emv standards by debuging or updating software

    最終設計好的智能卡介面（ sci ）模塊被集成到晶元內部，減少了整機體積和成本，此外， sci內部具有多個可編程寄存器，使得它具有很強的兼容能力，除了支持基於iso7816協議的智能卡外，通過軟體的調試和升級能夠支持包括基於gsm 、 emv等協議的智能卡。
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