字時比較器 的英文怎麼說

中文拼音 [zìshíbǐjiàoqì]
字時比較器 英文
time comparator word
  • 字 : Ⅰ名詞1 （文字） character; word 2 （字音） pronunciation 3 （字體） form of a written or printed ...
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 比 : Ⅰ動詞1 （比較; 較量高下、 長短、距離、好壞等） compare; compete; contrast; match; emulate 2 （比...
  • 較 : Ⅰ動詞1 （比較） compare 2 [書面語] （計較） dispute Ⅱ副詞（比較） comparatively; relatively; fair...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 比較 : 1 （對比） compare; compare with; contrast; parallel （with）; comparison; by comparison; in comp...
  1. The subject inducts digital time division technology ( pwm ), which is more advantageous at the accuracy and the predigest of hardware than simulant multiplication. what they call measuring power energy reasonably is that measuting except harmonics power energy fed back power. yet it realizes reasonable measurement of power energy which measures by base wave ac parameters method base on digital time division

    本課題引入了數字時分割（ pwm ）脈寬調制技術，在測量的準確性、硬體電路的簡化等方面都比模擬乘法器具有較高的優越性。所謂合理的計量電能，就是不計非線性負載回饋給電網的負的諧波電能，而採用基於數字時分割的基波交流參數測量的方法，真正實現了電能的合理計量。
  2. The high - speed digital signal processor is adopted and the real - time and reliability are improved greatly. the system with low - loss and high - efficiency is suitable for solar powered unmanned engine

    該系統採用高速數字信號處理器全數字化設計，其實時性好、可靠性高，並具有功耗低，效率高等特點，比較適合應用於太陽能無人飛機。
  3. In chapter 4 we discuss the design of the high speed and high performance vlsi and its imp1ementation, firstly we ana1yze and compare the features and ru1es of al1 kinds of fft algorithm, adopt complex radix 4 butterfly calcu1ation as basic alu, then discuss all kinds of process architectures, the design thoughts, rule, method, technique way, the characteristics of the design are r4 dit algorithm, pingpong ram design method and pipeline structure between stages. we also analyze the limited word length effect and the method to avoid overflow of the fixed points fft process, bring out the expandable platform mode

    第四章主要討論了高速高性能的快速傅立葉變換處理器的設計和實現，首先分析和比較了各種快速傅立葉變換演算法的特性和規律，提出基4蝶算的演算法具有最好的性價比，討論了順序、級聯、并行和陣列的處理結構，闡述了設計高速高性能快速傅立葉變換處理器時的設計原則、設計思路、所採用的技術路線，驗證並測試fft處理器，分析了定點fft處理過程由於有限字長效應所產生的量化誤差的范圍及防溢出控制辦法，提出了可擴展平臺模式。
  4. Because direct torque control requires very high performance of real - time, the popular microcomputer core dsp is used as controller in the design of hardware. its high speed of running is suitable for the experiment. in the main circuit, there is a highly integrated power element : ipm as inverter, which includes seven igbt, has high switch frequency and fault diagnosis function

    在本控制系統的具體實現上，由於直接轉矩控制對實時性要求很高，因此在硬體方面，採用了目前比較流行的數字信號處理器（ dsp ）作為系統的控制器，其處理速度高的特點正好符合本實驗的需要：在主電路中，本系統使用了集成度高的功率器件：智能功率模塊（ ipm ） ，作為逆變環節，其集成了七個igbt ，實現了高開關頻率逆變以及故障診斷的功能，從而使控制系統的體積大大縮小、控制更加靈活。
  5. Due to the direct torque control requires very high performance of real - time, the popular microcomputer core dsp is used as controller in the design of hardware. its high speed of running is suitable to the experiment. in the main circuit, there is a highly integrated power element : ipm as inverter, which includes seven igbt, has high switch frequency and fault diagnosis function

    在本控制系統的具體實現上，由於直接轉矩控制對實時性要求很高，因此在硬體方面，本課題採用了目前比較流行的數字信號處理器（ dsp ）作為本實驗的控制器，其處理速度高的特點正好符合本實驗的需要；在主電路中，本系統使用了集成度高的功率器件：智能功率模塊（ ipm ） ，作為逆變環節，其集成了七個igbt ，實現了高開關頻率逆變以及故障診斷的功能，從而使控制系統的體積大大縮小、控制更加靈活。
  6. In this position do sharp microrotations clockwise and counterclockwise. the focus bar has always to remain at most, while the digital comparator red reference does very small swings

    在這個位置對主軸做一下順時針和逆時針移動。聚焦條總是存在，當數字比較器的顯示紅色，存在一些小的震動時。
  7. With the focus bar at most, go on the most left point of the digital comparator and now stop the spindle rotation ; the focus bar has to be completely lightened and has not to switch on or off segments

    當聚焦條出現了絕大部分時，繼續向左移動數字比較器顯示值停止，停止主軸的旋轉；聚焦條完全的點亮並顯示在屏幕，並且中間沒有分割點。
  8. Equipment of power quality dynamic compensation control realization can be either digital or analogical. the advantage of digital compensation control ( dcc ) is that it can compensate harmonics to a precision level and is independent of the surrounding environment. but dcc need high - speed real - time chips to deal with digital signal processing, so it has high price

    電能質量動態補償裝置的控制是影響電能質量動態補償裝置的性能的重要因數，電能質量動態補償裝置的諧波補償主要有數字補償控制和模擬補償控制兩種，數字補償的優點是可以對電網諧波的補償達到很精確的程度，不容易受到外界運行環境的影響，但是要求運行速度很高的實時數字信號處理器，因此造價較高，模擬補償控制對硬體要求比較嚴格。
  9. In paper we designed the processing circuits of magnetic encoder, designed the magnified circuit, the signal collection circuit and the d / a conversion circuit are designed. then magnetic encoder can output two different type signals : digital signals and analog signals, the two type signals are corresponding

    對磁編碼器的信號處理電路進行了設計，設計了磁頭的放大比較電路、單片機信號採集電路和d a轉換電路，設計了單片機信號採集和d a部分的程序，使編碼器能在輸出數字信號的同時輸出與數字信號一一對應的模擬信號。
  10. After compared lots of literatures and methods, we offer the norm for selecting different filters. that is to say, in arrhythmia analysis, the integer coefficient lowpass filter is adopted, while in heart rate variability analysis, the high pass filter designed by all - pass minus low - pass filter or filter which can remove both baseline wander and 50hz power - line frequency at one time is used

    在對大量文獻進行比較、研究的基礎上，針對不同的臨床應用目的，提出了各種濾波器的選用準則：在心律失常分析中選用整系數低通數字濾波器對原始心電信號進行濾波；在對心率變異信號進行分析時需先用低通濾波器濾波然後再採用全通減低通方法設計的高通濾波器或者一次性濾波器進行濾波。
  11. The project is to develop the 100mhz wideband digital storage oscilloscope ( wdso ) ， typical performance character : input signal - 3db bandwidth is 100mhz, real time sampling frequency is 20msa / s, equivalent sampling frequency is 10gsa / s, resolution is 8bits, dual signal channel, and delicacy is 5mv 5v div per channel ， time sweep velocity is 2. 5ns - - 5s div 。 so the project is provided with higher performance - to - price ratio, stronger competitive capacity in market and widest applied foreground at the area of wdso

    本次課題的具體目標是實現100mhz帶寬的數字存儲示波器正樣機的研製，具體主要性能指標達到最高實時采樣率20msa / s 、等效采樣率10gsa / s 、被觀測信號3db模擬帶寬達100mhz 、采樣數字解析度8bit ；雙通道，幅值靈敏度： 5mv 5v div ，掃速2 . 5ns - - 5s div 。該方案具有較高的性價比，較強的市場競爭力和廣闊的應用前景。
  12. Design a kind of sub - optimum digital prefilter. through the simulation of timing recovery loop which is n ' t added prefilter and which is added prefilter, discuss the convergence characteristic and compare the relation between timing jitter and signal to noise ratio, the relation between timing jitter and noise bandwidth of loop, the relation between symbol error ratio and signal to noise ratio

    通過對加預濾波器后的定時恢復環的模擬，討論了環路的收斂情況，比較了所設計的數字預濾波器和無預濾波器時環路定時抖動與信噪比、定時抖動與環路噪聲帶寬、誤碼率與信噪比的數量關系，證實所設計的數字預濾波器對減少定時抖動非常有效。
  13. This thesis deals with design and application of a multiprocessor made of four dsps in monitoring receiver. the broadband monitoring receiver requires a kind of chip with high performance because of complicated intermediate frequency signal processing. the author selects a kind of digital signal processor called adsp21160. during the process of design, the author uses cpld, fpga and some special cpus to finish signal, processing in the monitoring receiver. cluster multiprocessor based on vxibus made of four adsp21160 is put forward. the task distribution of four dsps is solved too. furthermore, data transition methods between chips at a high speed through link ports and chip extension mode using external port are recommended. the author debugs, emulates the program in one adsp - 21160 ez - kit lite and simulates the multiprocessor program in visualdsp + +

    本文主要探討了監測接收機中多dsp處理模塊的設計與應用，寬帶監測接收機的中頻處理數據量大、實時性高，這樣，對dsp晶元提出了很高的要求，作者通過比較選擇了最適用於監測接收機的數字信號處理器adsp21160 ，並結合使用了cpld 、 fpga以及一些專用的cpu來完成監測接收機中的數據處理。作者提出了由四片adsp21160組成的簇式多dsp處理模塊的結構並配以了vxi總線，論述了簇式結構的特點，解決了多dsp處理模塊中四片adsp21160的任務分配問題。
  14. Results from hspice simulation and foundation show that the band - gap voltage reference of ic is 3. 126v, has a psrr of 65db, an accuracy of 23ppm / in [ 0, 70 ], and the band - pass filter has an gain of 73db, whose band - pass frequency is 0. 1hz ~ 10hz. comparator ’ s window is 700mv. time sequence and functions of digital circuits are normal

    Hspice和foundation軟體模擬的結果顯示，帶隙基準電壓源為3 . 126v ，電源電壓抑制比為65db ，溫度系數為23ppm / ;帶通濾波放大部分增益為73db ，帶通頻率為0 . 1hz ~ 10hz ;雙限電壓比較器窗口為700mv ，功能良好，數字電路時序正確，功能正常。
  15. The proposed algorithm lows the complexity by choosing decision delay in advance and then making solution of the equalizer tap coefficient, a new decision delay choice method is proposed, solution by using weight method, diagonal matrix transform, z extension and a new energy restrictive condition which restrains noise enhance, a new decision delay choice method is proposed, the simulation result shows that the proposed algorithm has better equalization effect and enhanced performance comparing to the general mmse algorithm, simulation research on the precision and dynamic scope of parameters in digital realization time domain equalization algorithm, design software and hardware of time domain equalizer. fourthly, there exist a lot of interfere in dsl line, especially, dsl works in multi - user mode, the near end interference is serious

    通過先選擇判決時延，再進行時域均衡器抽頭系數求解的方法降低了時域均衡計算復雜度；對于均衡器抽頭系數的求解使用了加權技術，通過對角矩陣變換， z擴展，使用不同的能量約束條件對演算法求解，結果表明這種約束有效的抑制了噪聲增強，與常用刪se比較，該演算法有更佳的均衡效果，演算法性能得到了提高：論文還對數字化實現時域均衡演算法中每一部分參數的精度、變量的動態范圍進行了模擬研究，對時域均衡的軟硬體實現進行了設計。
  16. As an vxi equipment designed for testing complex data system, it wins through the shortcomings of traditional test method which uses signal generator to supply stimulus and utilizes logical analyzer to sample response data. it can achieve complicated cooperation between stimulus and response by sampling response data in the single period and then comparing it with the expectation data while imposing test stimulus on the test objective

    它是為滿足復雜數字系統的測試需要而設計的vxi器件，克服了用數字信號發生器提供激勵並使用邏輯分析儀採集響應數據這種傳統測試手段的不足，在激勵和響應之間實現復雜的聯動配合，將測試激勵施加於被測對象的同時，在單周期內採集響應數據並與預期數據實時比較。
  17. The query compiler uses this information while checking any character comparison operations, to decide how to evaluate the operations

    查詢編譯器在檢查字元比較操作時使用該信息，以決定如何執行操作。
  18. Then the author presents the structure and the working principle of digital loop carrier system, in other word, the application environment of quad el transceiver, and then the author highlights the role that quad el card plays in the whole system, consequently, the author introduces the systematical structure and features of arm embedded processor. concerning about the restrict requirement of time during data transmission, the author of this paper also introduces the fpga technology, which is used mainly for providing the system with accurate time

    接著敘述了數字環路系統的結構和工作原理，即四路e1收發器的應用環境，著重介紹了四路e1板卡在整個系統中所扮演的角色和嵌入式處理器arm的體系結構和特點，鑒于數據傳輸中對時鐘的要求比較嚴格，本文還介紹了fpga技術，應用它主要是為系統提供各個精確的時鐘。
  19. Time comparator, word

    字時比較器
  20. This high speed digital test module is based on the vxi bus structure and specified on multi - channel and high speed aspects ; it is also capable of generating the stimulant signal and collecting the responded data ; meanwhile because the relationship between stimulation and response can be programmable, the module is highly intellective and it helps the testing system work more automatically ; what ' s more, with the good functions like real - time comparison, branch, single step, pause, trigger, it makes the testing more efficient as well

    本實驗室設計實現了高速數字測試模塊，該模塊是採用vxi總線結構的儀器，具備以下功能:多通道，高速度;同時具備產生激勵信號和採集響應數據的能力;能夠通過編程在激勵和響應之間建立起因果聯系，使整個測試過程體現出一定的智能性，大大提高測試系統的自動化程度;具有實時比較，實時跳轉，單步，暫停，觸發等功能，使測試過程更加快速和靈活。
分享友人
分享到 Line

分享到臉書