字譯碼器 的英文怎麼說

中文拼音 [zìyìmǎqì]
字譯碼器 英文
word decoder
  • 字 : Ⅰ名詞1 （文字） character; word 2 （字音） pronunciation 3 （字體） form of a written or printed ...
  • 譯 : 動詞（翻譯） translate; interpret
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  1. The contents adds the to code the system ". the colloquy dvd sees the arithmetic figure to add the project. only the that the dvd that css admit to broadcast the to can just break password see data

    「內容加密編碼系統」 。正式的dvd視頻數字加密方案。僅css許可的dvd播放器才可以破譯視頻數據的密碼。
  2. The control unit decodes the eighteen bits, so that the computer knows what we want it to do next.

    控制器對這18位字進行譯碼，於是計算機就知道我們要它下一步做什麼。
  3. When there are less random errors in the channel, inner code can be utilized to correct them ; when there are lasting accidental errors or too many random errors beyond the inner code ' s capacity,

    當通道產生少量的隨機錯誤時，通過內碼就可以糾正。當產生較長的突發錯誤或隨機錯誤很多，超過內碼的糾錯能力，則內譯碼器產生錯譯，輸出的碼字有幾個錯誤。
  4. Common interface specification for conditional access and other digital video broadcasting decoder applications ; german version en 50221 : 1997 corrigendum : 2000

    有條件存取和其它數字電視廣播譯碼器用共用介面規范
  5. The design and application of ad6640 and ad6624 are fully discussed in this part. the design of software module includes the parameter design for ddc filter and the baseband signal processing of dsp. and the realization of the viterbi channel decoding algorithm by dsp and the simulation of the burst at the transmitter are discussed

    模塊的硬體設計主要包括： a d轉換器、數字下變頻器（ ddc ）以及dsp ，詳盡討論了a d器件ad6640和ddc器件ad6624的設計和應用；模塊的軟體設計主要包括： ddc濾波器參數設計和dsp的基帶信號處理，給出了viterbi通道譯碼演算法dsp實現和發射端突發形成的模擬實現。
  6. Common interface specification for conditional access and other digital video broadcasting decoder applications

    條件存取和其它數字視頻廣播譯碼器用通用介面規范
  7. This is the core of the issue. in this section we designed the cells of the dac, including the decoder circuit, bandgap reference voltage circuit, current source circuit and switched circuit etc. the fourth chapter the simulations of circuit and errors of the dac are discussedi, so the simulation waveforms are plotted on the paper and we must take the error corrections and minimize ways

    對于整個d a轉換器的具體結構和電路設計放在第三章，這也是本文的核心之處，對d a轉換器的整體電路及主要電路單元如：數字譯碼電路、帶隙參考電壓源電路、電流源產生電路、差分電流開關電路等進行詳細地分析和設計。
  8. Enhanced variable rate codec speech service option 3 for wideband spread spectrum digital systems

    寬帶頻譜擴展數字系統用增強的可變率編譯碼器語音服務選擇3
  9. Evrc 3 software distribution for tia - 127 - a - enhanced variable rate codec speech service option 3 for wideband spread spectrum digital systems

    Tia - 127 - a的軟體配置.寬帶頻譜擴展數字系統用增強的可變率編譯碼器
  10. This code causes an error because the compiler terminates the string after the second quotation mark, and the remainder of the string is interpreted as code

    此代碼會導致錯誤，因為編譯器將在第二個引號之後終止字元串，並將字元串的其餘部分解釋為代碼。
  11. The whole paper had been divided into four parts : the first part introduces the general situation of digital trunking system and its channel encoding, the recent development of viterbi decoding ; the second part studies the error control scheme, and the convolution decoding depth which is most fit to digital trunking system ; the third part introduces several low power viterbi decoder and its principle ; the last part proposes a united - decision estimating viterbi decoding algorithm

    本文共分為四部分，第一部分介紹了數字集群及其通道編碼的總體情況， viterbi譯碼的發展現狀。第二部分給出了數字集群系統中話音通道差錯控制總體方案，並研究了適合數字集群系統的卷積碼的解碼深度。第三部分簡單介紹了各種低功率viterbi譯碼器及原理。
  12. Both are used to separate the responsibility for rendering pages from the model and controller. both accept objects passed into them as an input argument, both allow inserting string values within code " expressions ", and allow direct use of java code to perform loops, declare variable, or perform logical flows " scriptlets ". both are good ways of representing the structure of a generated object web page, java class, or file while supporting customization of the details

    Jet與jsp非常類似：二者使用相同的語法，實際上在後臺都被編譯成java程序；二者都用來將呈現頁面與模型和控制器分離開來；二者都可以接受輸入的對象作為參數，都可以在代碼中插入字元串值（表達式） ，可以直接使用java代碼執行循環、聲明變量或執行邏輯流程式控制制（腳本） ；二者都可以很好地表示所生成對象的結構， （ web頁面、 java類或文件） ，而且可以支持用戶的詳細定製。
  13. The paper is completed research of measurement and control system based on dsp under technology. the paper is designed a card with the data - collection conversion and control by adopting mainly tms320f240 among the dsps as kernel processor, with peripheric a / d and d / a circuit epm7128 ' s decode and latch circuit and isa interface circuit

    本論文主要是採用數字信號處理器dsp中的tms320f240作為核心處理器，結合外部的模數轉換和數模轉換電路、可編程邏輯器件epm7128的地址譯碼和鎖存電路和isa介面電路，設計了集採集、轉換、控制於一身的isa卡。
  14. The fifth chapter analyzes the fixed - point error of bp - based and normalized bp - based decoding algorithm, and gives the final simulation results of each decoding algorithm. with the simulation results and the considering the tradeoff between hardware complexity and error performance, some key parameters and finite precision analysis for the hardware implementation of ldpc decoder have been performed

    第五章對bp - based和normalizedbp - based演算法進行了定點模擬，對ldpc譯碼器的關鍵參數、硬體實現中的定點量化與字長精度問題進行了深入的研究，給出了對譯碼器硬體實現具有參考意義的研究結果。
  15. This paper achieves expected digital filters program through algorithms descriptions, analyzing and realization, simulation, comparing on error and speed. this paper achieves expected digital interpolations program through algorithms descriptions, analyzing and realization, simulation, comparing on error and speed

    本文應用matlab信號處理工具箱，通過對數字濾波器演算法的描述、演算法分析、實驗模擬、誤差比較，及性能比較，最終獲得滿足要求的數字濾波程序，並編譯成c + +源代碼文件配合主程序調用，完成了系統聯調。
  16. After a great amount of detailed computer simulations and concise qualitative and quantitative theoretical analysis, the turbo codes " parameters and fpga specific hardware implementation architecture suitable for being integrated into dtv systems are determined. furthermore, the codec is completely designed with verilog hdl, ending with an occupation of less than a 600 - thousand - gate fpga chip. at this lowest hardware cost, a white noise snr threshold of 1. 8db at a net stream rate of 6mbps is achieved, which exceeds all other existent dtv systems " performance

    經過大量詳細的計算機軟體模擬和簡明扼要的定性與定量的理論分析，最終確定了數字電視系統中適合採用的turbo碼參數及針對fpga特殊構架的硬體實現結構，並用verilog硬體描述語言完成了turbo碼編譯碼器的完整設計，以佔用不到一片60萬門fpga晶元的較少的硬體資源取得了在6mbps凈碼率下1 . 8db的白噪聲信噪比門限這一遠遠超過現有任何數字電視系統的性能。
  17. Then, memory cell array and some parts of peripheral circuits used in sram, for example, sense amplifyier and adderss decoder, are designed and verifyied by simulation. furthermore, some novel methods, such as clocked hierarchical word decoding structure, multi - stage sense amplifyier, common data line and data bus equlibruim technology has been applied in the design of 128kbit and imbit sram. what ' s more, we have studied compiler technology applied in the designing course of a imbit full cmos sram from the pointview of methology

    然後對sram的存儲單元電路以及外圍電路中的靈敏放大器和地址譯碼器進行了設計和模擬，在此基礎上，以128kb和1mb全cmossram設計為例，從方法學角度對同步sram設計中的帶時鐘分等級字線譯碼，多級靈敏放大和位線及總線平衡等技術進行了研究，並給出了相應的compiler演算法。
  18. The two methods, an all - parallel viterbi decoder and an optimized viterbi decoder are represented. the former one is small constrained, simple construction and large resource consuming while the latter one is long constrained, complicated construction and small resource consuming. employing the digital circuit optimize algorithm, the latter one has already covered design thoughts of present viterbi decoder

    對于viterbi譯碼器，描述了適用於小約束度、結構簡單、資源耗費較大的全并行viterbi譯碼器和使用於大約束度、結構復雜、資源耗費較小的優化viterbi譯碼器，其中，優化viterbi譯碼器採用viterbi譯碼優化演算法和數字電路設計的優化演算法，基本已涵蓋了當前viterbi譯碼器的設計思路。
  19. D a decoder

    數字模擬譯碼器
  20. In order to implement the iess 309 standard and sequential decoding for the convolutional codes in satellite digital receiver, we have made a deep research in sequential decoding algorithm and solved some problems on implementing the sequential decoder for convolutional codes

    為了實現iess309協議標準，在衛星數字接收機中實現卷積碼的序列譯碼，我們深入的研究了序列譯碼演算法，解決了序列譯碼器實現的過程中存在的一些問題。
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