指令流水線 的英文怎麼說

中文拼音 [zhǐlìngliúshuǐxiàn]
指令流水線 英文
instruction pipeline
  • 指 : 指構詞成分。
  • 流 : Ⅰ動1 （液體移動; 流動） flow 2 （移動不定） drift; move; wander 3 （流傳; 傳播） spread 4 （向壞...
  • 水 : 名詞1 （由兩個氫原子和一個氧原子結合而成的液體） water 2 （河流） river 3 （指江、河、湖、海、洋...
  • 線 : 名詞1 （用絲、棉、金屬等製成的細長的東西） thread; string; wire 2 [數學] （一個點任意移動所構成的...
  • 指令 : 1 （指示; 命令） instruct; order; direct2 （上級機關對下級機關的指示） instructions; order; direc...
  • 流水 : 1 （流動的水） running water; stream2 （舊時指商店的銷貨額） turnover （in business）流水搬運作用...
  1. Research on instruction parallelism - based software pipeline

    基於指令并行的軟體流水線研究
  2. The crucial trait of risc architecture is that it can fit the pipeline compatibly

    Risc體系結構的重要特點是其便於利用流水線結構進行指令操作。
  3. It has five parts, such as integer execution unit, floating point unit ( fpu ), instruction cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way. the instruction set and i / o signals are compatible with powerpc

    它由定點執行單元、浮點單元、指令cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令，指令集和介面時序兼容powerpc ，是典型的risc微處理器結構。
  4. The risc mcu core is based on harvard architecture with 14 - bit instruction length and 8 - bit data length and two - level instruction pipeline the performance of the risc mcu has been improved by replacing micro - program with direct logic block

    設計的riscmcu採用14位字長指令總線和8位字長數據總線分離的harvard結構和二級指令流水設計，並使用硬布線邏輯代替微程序控制，加快了微控制器的速度，提高了指令執行效率。
  5. The paper elaborates risc technology characteristic and 5 - stage pipeline architecture and function of the 64 - bit risc cpu, and dwells on 64 - bit vega cpu characteristic, and details the eda technology and the main flow of asic design, and elaborates the operation and exception process of the vega cpu and virtual instruction address " architecture and generation, and details cache architecture and mmu. the master dissertation dwells on virtual address translating into physical address, instruction cache finding address and instruction fetching, too

    詳細的闡述了64位vegacpu的特點，闡述了eda技術和asic設計的主要流程，闡述了vegacpu流水線結構、流水線操作、流水線暫停和異常處理，虛擬指令地址的結構和產生， mmu結構，包括指令tlb結構和虛擬指令地址向物理指令地址的生成流程， cache結構，尋址原理和指令的寫策略，指令高速緩存的尋址原理和結構，以及指令的獲取流程。
  6. The aim of mips pipeline is that one instruction completed in one period averagely

    Mips流水線的設計目標是要達到平均每個時鐘周期完成一條指令，這就是流水線的極限速度。
  7. Pipeline increase the cpu efficiency greatly, but the exist of instruction correlation make the pipeline block and delay frequently, as a result it can ’ t achieve the aim that one instruction completed in one period averagely

    但由於流水線中指令相關等問題的存在，常常使流水線發生阻塞延遲，使得指令不能夠在預定的時刻完成，因而無法達到極限速度的目標，更無法超越該速度。
  8. In order to enhance coding / decoding speed, we have rewritten image wavelet decomposition and composition program with c6701 assembly language in which we made use of parallel instructions and pipeline optimizing skill to lessen calculating time

    為了提高編解碼速度，圖像小波分解與合成程序完全用c6701匯編指令編寫，其中大量使用并行指令和流水線優化，使運算時間大大減少。
  9. Design of 3 - stage instruction pipeline 51 core

    一種採用3級指令流水線的51內核設計
  10. Reducing pipeline delay using two instruction fetching units

    通過兩個取指令部件消除流水線控制相關延遲
  11. The armp, which is controlled by a pipeline mechanism, has excellent real time performance and supports precise interrupt. the armp is compatible to powerpc 603e instruction set architecture ( isa ), and will be implemented by 0. 25 m cmos technique

    該處理器具有自主版權，採用自主設計的流水線結構進行控制，具有優良的實時性和精確中斷的特點，在指令集上與powerpc603e指令集完全兼容。
  12. ( 2 ) research the instruction launch strategy, controls correlation processing and data correlation processing of 32 - bit mips ’ s double - launching pipeline. obtained the design modes : static launch, optimized compile instruction, 1st pipeline jump and branch processing and double pipeline four channels front data path. ( 3 ) achievement designs by the platform xilinx ise 5. 2i, uses the verilog hardware description language to carry on the design description to the double - launching

    （ 2 ）對基於32位mips架構雙發射流水線的指令發射策略、控制相關處理和數據相關處理等流水線結構的重要問題進行深入研究，並得出了靜態發射、優化編譯指令序、第一流水線無延遲分支處理和雙流水線四通道前向數據通路等一系列能夠與32位mips架構相匹配的雙發射流
  13. For the real time performance need of the low speed speech compress algorithm and the asic implement of the transfer process between programs, the design is put forward in the paper, in which state registers control the cross access between operator and memory, register windows are used for the parameters transfer, and the technique of hardware controlling is used to avoid pipeline conflict, so that the main problems of the transfer process in tr600 are solved effectively

    摘要針對低速率語音壓縮演算法對處理器系統實時處理復雜運算的性能要求，就程序調用過程的asic實現問題進行了對比與分析，進而提出了用層次狀態寄存器控制存取運算元對存儲體交叉訪問的方法，並結合運用寄存器窗口傳遞參數的功能，以及利用空指令硬布線處理流水線沖突的方法，有效地解決了tr600晶元中調用過程存在的主要問題。
  14. In a multithreaded microprocessor which has a superscalar execution core, with the issue width being larger and the pipeline getting deeper, the misprediction penalty will become longer

    在執行單元為超標量結構的多線程處理器中，轉移誤預測損失會隨著指令發射帶寬和流水線級數的增加而增加。
  15. When transmitting or receiving data from moving machine part, it is of great advantage to use wireless communication. in the future, machines assembling products might be able to communicate with the product without physical connection during the assembly sequence, performing tests and downloading software to the products

    未來，藍牙還可以用到流水線上對產品的操作，通過藍牙無線指令傳輸，生產機器將不必通過直接的接觸，而可以在有效的距離范圍內，對產品進行遠程的測試或驅動軟體的加載。
  16. It applies multiple clocks on different pipeline parts basing on their logic complexity, and provides a parallelism on the slow part for throughput compensation

    它允許流水線模塊根據各自邏輯復雜度選擇不同的工作頻率；通過提高簡單模塊的工作頻率，並增加復雜模塊的并行度，以實現流水線的指令吞吐率的優化。
  17. It is a risc microprocessor, has a six - stage pipeline, with separated data cache and instruction cache

    銀河ts - 1採用典型的risc結構，六級流水線，具有獨立的指令cache和數據cache 。
  18. This processor processes 9 - stage pipeline, and risc instruction set. its operation frequency is capable of achieving over 150mhz

    該數字信號處理器的cpu具有先進的vliw結構內核、九級流水線，具有類似risc的指令集，它的工作頻率可達到150mhz以上。
  19. And hardware / software coverification is carried out to guarantee the correctness of design. in the design of hardware of memory system, according to the system specification, we select the appropriate memory capacity, sram block, associativity and the placement of cache in the pipeline

    在存儲系統的硬體設計中，始終以性能指標作為依據，克服了存儲器容量、庫單元規格選擇、聯合度的選擇和cache在流水線中的位置選擇等困難，設計出了符合指標要求的指令存儲系統。
  20. This is a really great feature if your software is designed to be used on a multiprocessor machine if the software is open source, it will probably end up running on quite a few of these

    那樣可能涉及在指令流里移動指令要比所要求的移動時間還要發生得早，這樣做可以使在cpu等待內存完成讀寫時避免流水線的延遲。
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