指令集結構 的英文怎麼說

中文拼音 [zhǐlìngjíjiēgòu]
指令集結構 英文
architecture instruction set
  • 指 : 指構詞成分。
  • 集 : gatherassemblecollect
  • 結 : 結動詞（長出果實或種子） bear （fruit）; form （seed）
  • 構 : Ⅰ動詞1 （構造; 組合） construct; form; compose 2 （結成） fabricate; make up 3 （建造; 架屋） bui...
  • 指令 : 1 （指示; 命令） instruct; order; direct2 （上級機關對下級機關的指示） instructions; order; direc...
  • 結構 : 1 （各組成部分的搭配形式） structure; composition; construction; formation; constitution; fabric;...
  1. It has five parts, such as integer execution unit, floating point unit ( fpu ), instruction cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way. the instruction set and i / o signals are compatible with powerpc

    它由定點執行單元、浮點單元、指令cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令，指令集和介面時序兼容powerpc ，是典型的risc微處理器結構。
  2. Risc processors generally feature fixed - length instructions, a load - store memory architecture, and a large number of general - purpose registers and / or register windows

    Risc處理器一般的特徵是固定長度的指令集，一個負載儲備存儲結構，和大量通用寄存器，及寄存器窗口。
  3. In this paper, using a top - down design scheme, the risc mcu ip core is divided into two parts : data path and control path. all the modules in the two parts are described by verilog hdl, a kind of hardware description language. the simulation and synthesis of the whole work are finished successfully with eda tools

    本文對pic16c6x單片機系統結構、指令系統和系統時序進行了分析，並且在此基礎上對精簡指令集mcuip核進行頂層功能和結構的定義與劃分，建立了一個可行有效的riscmcuip核模型本文將mcuip核劃分為數據通道與控制通道兩部分，採用asic設計中的高層次設計方法，使用硬體描述語言veriloghdl對這兩部分的各功能模塊進行了設計描述；利用多種eda工具對整個系統進行了模擬驗證與綜合。
  4. The armp, which is controlled by a pipeline mechanism, has excellent real time performance and supports precise interrupt. the armp is compatible to powerpc 603e instruction set architecture ( isa ), and will be implemented by 0. 25 m cmos technique

    該處理器具有自主版權，採用自主設計的流水線結構進行控制，具有優良的實時性和精確中斷的特點，在指令集上與powerpc603e指令集完全兼容。
  5. With the popular sources and models of static power fully discussed at first, the stack effect of transistor - level and logic - level cmos circuits are analyzed in detail according to the broadly adopted uc berkeley bsim model

    這是一款risc指令集的低功耗處理器晶元，它採用哈佛總線結構，兼容了avr指令集，具有4kb片內sram ， 128kbflash （暫時處于片外） ，除了
  6. This architecture became known as risc reduced instruction set computer

    這種體系結構稱為risc （精簡指令集計算機） 。
  7. This paper mainly focuses on the following three field : system structure, system hw / sw ( hardware / software ) partition. synthesis and verification. and presents a hw / sw co - design method based on ip ( intellectual property ) core. we use this method to design asip, and verify this virtual machine using instruction codes, ac - 3 codes and ts ( transport stream ) flow

    本文從晶元系統的整體入手，重點從系統的結構、軟硬體分割以及晶元系統的設計驗證三個方面對該晶元系統的設計做了深入的研究，提出了一種基於ip核的軟硬體協同設計方法，運用該方法對asip進行設計，並採用虛擬機的模型，採用指令集程序、 ac - 3解碼程序、 ts流程序進行模擬驗證。
  8. A bus shared heterogeneous architecture consisting of one or more instruction set processor cores, one or more dedicated hardware ip cores and one or more on - chip memories usually provides a good solution

    基於總線互連的由一個或多個指令集處理器核、一個或多個專用硬體ip核、一片或多片片上存儲器構成的異質體系結構成為媒體系統晶元的合理選擇。
  9. This paper presents the yh ts - 1 instruction architecture, which based on the vector expansion of arm v4 instruction architecture. it supports vector processing and scalar processing in the same instruction set

    本文提出了基於armv4指令集體系結構擴展的銀河ts - 1指令集體系結構，在同一個指令集內同時支持標量機制和向量機制。
  10. Ibm scientists and engineers have garnered recognition for discoveries and inventions in fields as diverse as reduced instruction set computers risc, database management systems, logic and complexity theory, nanostructured materials, high - temperature superconductivity, and laser surgery, among many others

    Ibm的科學家和工程師們在簡化指令集計算機（ risc ） 、數據庫管理系統、邏輯與復雜性理論、納米結構材料、高溫超導、激光外科以及很多其他的領域上的發明和創新受到了人們的表彰。
  11. They could be partitioned two sorts by structured computer organization. one is complex instruction set computer ( cisc ), another is reduced instruction set computer ( risc )

    Cpu的分類方法很多，最為典型的是按照體系結構把它們分為復雜指令集處理器（ cisc ）和精簡指令集處理器（ risc ） 。
  12. In order to generate the exact set of the host processor s instructions, the jit compiler needs to precisely determine the architecture type of the underlying processor

    為了生成主機處理器的正確的指令集， jit編譯器需要明確地確定底層的處理器的體系結構類型。
  13. You also need to know whether the jvm correctly determines host processor architecture so that the jit compiler can produce the correct set of instructions for that architecture

    您還需要知道jvm能否確定主機處理器的體系結構，以使得jit編譯器可以為那個體系結構生成正確的指令集。
  14. Traditional reduced instruction set computer ( risc ) and digital signal processor ( dsp ) have different application areas due to their different instruction set architecture ( isa ) and micro - architecture

    傳統的精簡指令集處理器（ risc ）和數字信號處理器（ dsp ）各自具有不同的指令集結構和微結構特點，適合於不同的應用領域。
  15. We propose two implementations of momr : one employs only hardware changes while the other uses instruction set architecture support. we show that momr execution leverages available resources in typical multi - issue processors with minimal additional cost

    我們提出了momr的兩種實現：一是利用硬體的改變而是使用instruction set architecture指令集體系結構，簡稱isa的支持。
  16. The powerpc architecture is organized into three instruction - set levels called " books. " book i is the base set of user instructions and registers that should be common to all powerpc implementations

    Powerpc體系結構的指令集分為三級，稱為「 books 」 。 book i是基本的寄存器和指令集，所有的powerpc實現都通用。
  17. And some low power considerations in data path design and on - chip memories design have also been taken. the mac operation is essential to media processing

    Md32的指令集中包括大量simd （ singleinstructionmultipledata ）結構的多媒體擴展指令， alu模塊是其主要的硬體支持部分。
  18. In the process of selection about cpu, i compared several projects, and select the project of " mcu based risc technology " to research. the project apply the mpc555 chip of motorola company. and emphasize to research the application of spi and canbus. 4. as the part of the hardware platform, the i / o model block is researched, and some new hardware design and selfchecking measure applied in it

    3 .在邏輯運算模塊中，對保護cpu提出了幾種方案進行了比較，本文採取了"基於risc （精簡指令集結構）技術的微處理器"方案進行研究，該方案採用的是motorola公司的mpc555晶元，並重點對spi （串列外圍介面）和canbus現場總線在硬體平臺中的應用進行了探討。
  19. This processor processes 9 - stage pipeline, and risc instruction set. its operation frequency is capable of achieving over 150mhz

    該數字信號處理器的cpu具有先進的vliw結構內核、九級流水線，具有類似risc的指令集，它的工作頻率可達到150mhz以上。
  20. The research work introduced in this paper mainly concerns the processor core design for media soc. media enhancement backward extension to mips - i compatible isa is presented in this paper. based on the analysis of inherent characteristics of media application algorithms, the basic mips - i compatible isa is extended to support sub - word parallel simd operation, special result handling, and dedicated media instructions

    在國家863計劃的支持下，我們開展了系統晶元中媒體增強的數字信號處理器核的設計研究，本文作為部分成果，著重探討了處理器核指令集結構的媒體處理增強、處理器核微結構的設計和優化以及系統總線設計和媒體數據流調度的問題。
分享友人
分享到 Line

分享到臉書