數字邏輯門 的英文怎麼說

中文拼音 [shǔzìluómén]
數字邏輯門 英文
digital logic gate
  • 數 : 數副詞（屢次） frequently; repeatedly
  • 字 : Ⅰ名詞1 （文字） character; word 2 （字音） pronunciation 3 （字體） form of a written or printed ...
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 門 : Ⅰ名詞1 （房屋、車船等的出入口 ） entrance; exit; door; gate 2 （形狀或作用像門的東西） switch; va...
  • 數字 : 1. （表示數目的文字; 表示數目的符號） figure; digit; numeral; character; numeric character 2. （數量） quantity; amount
  • 邏輯 : logic
  1. Thirdly, the paper researchs the application of single electron transistor and the synthesis theory of cicuit based on quantum dot cellular automata by synthesis example of quantum cellular neural network based on build schr ? dinger equation of coupling quantum dot. at last, the paper researchs digital integrated circuit design based on quantum dot cellular automata and design a 8 - bit quantum dot cellular adder by qcadsign based on a method of majority logic reducetion for quantum cellular automata, it prove this designer of 8 - bit quantum dot cellular adder is correctly

    Dinger ）方程為基礎的量子點細胞自動機電路綜合理論，本文以量子細胞神經網路為綜合實例，建立耦合量子點的薛定鄂（ schr ? dinger ）方程組，通過化簡得到類似細胞神經網路的非線性電路方程。最後研究了基於量子點細胞自動機數字集成電路設計，通過建立邏輯方程，簡化邏輯方程，並設計基於精簡qca擇多邏輯門8位加法器，並用qcadesign進行了模擬，實驗證明設計正確性。
  2. The teaching difficulty of the course of digital circuit basis mainly focuses on some knowledge of components, for example, semiconductor basis, separation and integration logic gate circuits

    摘要《數字電路基礎》課程的教學難點主要集中在半導體基礎、分立和集成邏輯門電路等元器件知識部分。
  3. Finally the module is accomplished successfully after installation and debugging. it mainly consists of the minimum system of dsp, a / d conversion circuit, cpld control logic, watchdog circuit, op amplifier and filter circuit

    該模塊主要由數字信號處理器最小系統、模數轉換電路、復雜可編程邏輯器件控制邏輯、看門狗電路、運算放大器電路和模擬濾波器電路構成。
  4. With the rapid development of semiconductor, digital integrated circuit ( p, memory, standard logic gates, etc. ) and advance computer technology, the various measuring instruments ( virtual instruments ) with the powerful function of pc are produced in different industrial and scientific research fields. as we all known, the traditional instruments are usually built with discrete components and small scale ics, the disadvantages are obvious in system design, debugging and maintenance

    隨著半導體技術與數字集成電路（微處理器、存貯器以及標準邏輯門電路等）技術的迅速發展，特別是隨著計算機技術的發展，在工業生產和科學技術研究的各行各業中，人們利用pc機的強大處理功能代替傳統儀器的某些部件，開發出各種測量儀器（虛擬儀器） ，傳統儀器的數字邏輯部分多是採用分立集成電路（ ic ）組成，分立ic愈多，給系統的電路設計、調試及維護帶來諸多不便。
  5. In order to resolve the contradiction between real - time and arithmetic complex in the television tracking capture system, the paper designs the real - time target track processing system which is constructed by the high performance dsp chipset tms320c6416 as the core digital processor, the huge reprogrammable logic chipset cpld as the system logic control and the field reprogrammable array fpga as the image preprocessing chipset to sampled video digital image

    摘要為解決電視捕獲跟蹤瞄準系統中系統的實時性與演算法復雜性之間的矛盾，設計了以高性能的dsp晶元tms320c6416為核心處理器，結合大規模可編程邏輯器件cpld進行邏輯控制以及現場可編程門陣列fpga對採集的視頻數字圖像做預處理的實時目標識別跟蹤處理平臺。
  6. The real - time target track processing system is designed which is constructed by the high performance dsp chipset tms320c6416 as the core digital processor, the huge reprogrammable logic chipset cpld as the system logic control and the field reprogrammable array fpga as the image preprocessing chipset to sampled video digital image

    為了解決演算法復雜性及滿足工程實時性，設計了以高性能的dsp晶元tms320c6416為核心處理器，結合大規模可編程邏輯器件cpld進行邏輯控制以及現場可編程門陣列fpga對採集的視頻數字圖像做預處理的實時目標識別跟蹤處理平臺。
  7. Base on the theory analysis of the superconducting rsfq digital circuit model, wrspice is used to do time domain simulation of superconducting rsfq digital circuit in this paper, and superconducting jtl, buffer, rs flip - flop, t flip - flop, and or gate are acquired

    在超導rsfq數字電路模型的理論分析基礎上，論文中採用wrspice對超導rsfq數字電路進行時域模擬，得到了超導jtl傳輸線，緩沖器， rs觸發器， t觸發器，或門等基本邏輯單元電路以及電路參數。
  8. A distinguishable faults test generation method for digital circuits is presented. the features of basic gate circuits and neural networks are used to establish the test model, and to generate the test patterns for given faults. the fault model and constrained circuit are studied. some strategies, e. g, the reduction of the size of neural network, are proposed in order to accelerate test generation process. the experimental results demonstrate that the algorithm proposed in the paper is effective

    研究一種基於人工神經網路的能區分故障的數字電路測試生成方法，該方法利用電路基本邏輯門的特性和神經網路模型的特點，首先建立測試生成的神經網路模型，然後通過求解網路能量函數的最小值點獲得給定類型故障的測試矢量，其研究結果在可區分故障的測試生成方面提供了一種可能的新途徑
  9. Its intrinsic switching time is very short ; on the order of a picosecond. perhaps even more important is the low power dissipation ; superconducting circuits dissipate on the order of a microwatt per gate, a thousand times less than cmos circuits

    這種數字電子技術具有高速、低功耗的特點，使用基於rsfq技術的邏輯電路的時鐘頻率可達到幾百個ghz ，而功耗只有0 . 3微瓦門。
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