時序模擬 的英文怎麼說

中文拼音 [shíxùmónǐ]
時序模擬 英文
timing simulation
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 模 : 模名詞1. （模子） mould; pattern; matrix 2. （姓氏） a surname
  • 擬 : 動詞1. （設計; 起草） draw up; draft 2. （打算; 想要） intend; plan 3. （模仿） imitate
  • 時序 : [地質學] sequence; sequential; time sequence; timing sequence; sequence in time
  • 模擬 : imitate; simulate; analog; analogy; imitation; simulation模擬艙 boilerplate; 模擬電路 [電學] circ...
  1. Thus, the vhdl is carried to make a design for the forenamed algorithms, and the design is validated by simulation

    因此，本文用vhdl語言實現了ca邊緣檢測演算法模型的基本內核設計，並通過時序模擬，進行了演算法的硬體設計與效果驗證。
  2. Timing simulation for verifing the setup / hold time : 6

    存儲子系統的時序模擬。對tracecache技術進行研究。
  3. The design of this chip sticks to the general methodology of hdl design. lt is entered in hdl format with innoveda ' s visual hdl and simulated with modelsim simulator, after synthesized with fpga compiler ii, the edif is entered in quartus ii, which is supplied by altera corporation to place and route. the sdo file produced by quartus ii is backannotated to the netlists and timing - simulation is been done. the success of this cryptogrammic chip also shows the effectiveness and advantage of the methodology of high level design with hdl

    在innoveda的visualhdl設計平臺上用hdl語言完成了設計輸入，使用modelsim模擬器完成了功能模擬，使用synopsys的fpgacompiler進行了基於alterafpga庫的網表綜合，最後將edif網表輸入altera的布局布線工具quartus中進行了布局布線，將生成的sdo文件反標到modelsim模擬器中進行了時序模擬，該設計的成功，再一次表明了hdl設計方法的正確性和有效性。
  4. The hardware design which is the basis of the whole design based on sopc cooperates with the nios cpu to accomplish the functions of collecting ts information, detecting errors, and displaying information. the main content in this dissertation includes : ( 1 ) introducing the standard of mpeg - 2 system layer syntax and etr 290 standard about the three levels of detecting parameters ( 2 ) describing the structure and relationship of psi ; designing the hardware implement to accomplish the functions of collecting and analyzing ts information ( 3 ) analyzing and researching the three levels of detecting parameters to accomplish the partition of the hardware and software design, designing the detecting modules cooperated with the software and verifying the functions according to simulation ( 4 ) debugging and testing the design to verify it can achieve our requirements

    論文的主要內容包括: （ 1 ） mpeg - 2傳送流系統層的語法規范的介紹和dvbetr290標準中關于對碼流進行三層檢查和監測的參數的介紹; （ 2 ）描述了傳送流特殊信息之間的結構關系，介紹了用硬體方式實現碼流基本信息的提取的設計方法，並將這些信息提供給軟體進行分析處理和結果的顯示，從而實現對碼流提取和分析的功能; （ 3 ）對碼流的三層監測參數進行了分析研究，完成設計的軟硬體劃分，通過硬體設計方式完成對各個監測模塊的開發工作和時序模擬驗證，實現碼流監測功能; （ 4 ）介紹了對碼流基本信息進行提取、分析和碼流檢錯的硬體設計的調試情況和實驗驗證工作，以及最後與軟體設計部分進行聯合調試的情況
  5. The traditional simulation is based on the determinate environment. while the proposed jitter simulation environment is of a random processing, which is more closed to the real world

    傳統的時序模擬都是確定型的，而相位抖動的軟體模擬環境是一種隨機處理方式，它最接近真實的物理世界。
  6. It had also used vhdl language to carry through the timing simulation about hvct and digital clock. the simulation had the same result to the theory. it had established stability foundation to the future chip simulation

    並以實際應用為例，用其對高壓電流互感器和數字鐘進行了時序模擬，模擬結果與理論一致，為進一步的晶元模擬奠定了堅實的基礎。
  7. The main process includes following : system design, module design, function simulation, time simulation and hardware verification. the whole system is divided into several modules and each module is connected by signals, which based on the arithmetic of uart and the requirement of design. the module design is to design inner circuit structure of each module and uses verilog language to code the code

    系統設計是基於uart的實現演算法和設計指標要求，對系統劃分模塊以及各個模塊的信號連接;模塊設計是設計出每個模塊的功能，並用verilog一hdl語言編寫代碼來實現模塊功能;功能模擬和時序模擬使用的工具是以dence的nc _ veri109 ，首先對系統的每個模塊進行功能和時序模擬，模擬通過之後，將整個系統的代碼在外部的輸入埠加上激勵，對整個系統進行功能和時序模擬;硬體驗證是用fpga對系統進行了功能驗證。
  8. We have investigated domestic and foreign researches in computer simulation of relay control systems deeply ; and found there are two issues which haven ’ t been resolved perfectly : extracting electrical contact informations and simulating events ’ sequential - quality. we focused on these two issues and providing a better solution, the results are as follows : 1. we model electrical contacts as a switched network

    本文在對國內外繼電控制系統計算機模擬成果進行深入研究和分析的基礎上，針對繼電控制系統電氣聯系信息提取和事件時序模擬不夠完善的問題開展研究，給出了較好的解決方案，取得的成果如下: 1 .針對繼電控制系統包含大量開關元件的特點，將其電氣聯系抽象為開關網路。
  9. On the other hand, we accomplished the asic design flow successfully based on the fpga design. we have made the most use of various optimization methodology and simulation tools include dynamic simulation, static timing analyzing and post simulation. at last this design net list was past to layout design team in order to check its electronic characters

    在我們的asic流程中，首要的因素是在fpga驗證其正確性的基礎上對速度與面積進行科學有效的平衡，在成本和性能中間取得良好的結合點，運用先進的eda設計工具和演算法對設計進行綜合優化（ synthesis ） ，動態時序分析（ dynamicsimulation ） ，靜態時序模擬（ sta ）到自動布局布線（ apr ）之後將寄生參數反標回前面的步驟進行更精確的判斷和分析，最後交給版圖設計人員進行版圖設計和優化。
  10. Then the designs of modules mentioned in the scheme are discussed in detail. the main contents of the dissertation include : 1. to satisfy the need of a16 / d16 single - cycle and block data transfer capability, the method of the state machine and diagram are adopted. the arbiter, requester, interrupter, interrupter handler modules are also implemented by use of the state machine. these modules are verified theoretically by using timing simulation

    本文具體工作如下: 1 .用狀態機和電路圖的方式實現了vme總線a16 / d16單周期數據讀寫和塊傳輸功能;並用狀態機設計了vme總線請求器，總線仲裁器，中斷器和中斷處理器等，並進行了時序模擬。
  11. Its premise is pci bus specification and its sticking point is to analysis the function and architecture of pci bus controller. this dissertation finishes the design of pci bus controller, and it has also completed the function simulation of this module as well as timing simulation and a pcb card for test which prove it rightness at last

    通過本論文的研究，完成了pci總線控制器的設計，並且通過編寫測試激勵程序完成了總線控制器功能模擬，以及布局布線后的時序模擬，並設計了pcb實驗板進行了測試，證明所實現的pci目標控制器完成了要求的功能。
  12. Mostly, this design employs mentor corporation software " fpga advantage " as exploitation tool to perform design input 、 simulation and logic thesis with every level and every model to finish the fore design ； then, choices the xilinx corporation product xcv1000 of the vertex series and employ its tool “ allicance series ” to implement layout and timing simulation

    設計主要採用menter公司的功能強大的fpgaadvantage作為開發工具，進行了各個層次、各個模塊的設計輸入、模擬以及邏輯綜合，完成了電路的前端設計；然後選用xinlinx公司的fpga的vertex系列的xcv1000 ，用xinlinx公司的allianceseries工具，進行布局布線，然後再進行時序模擬，生成配置文件。
  13. Furthermore, timing simulation and static - state timing analysis were made. by doing these, netlist files were got

    並進一步做時序模擬和靜態時序分析，產生輸出網表文件，最後下載到fpga進行系統實現。
  14. Then describes the 4 function modules in vhdl, the vhdl programs have passed compile and debug in maxplus ii, the results of function simulation and timing simulation all prove that the design is correct, at last, maxplus ii generates a netlist file which can be download into chip

    然後使用vhdl硬體描述語言對四大功能模塊進行描述，在maxplus環境下編譯、調試通過，功能模擬和時序模擬結果證明設計正確，最後生成可下載的網表文件。
  15. Then has analysed function 、 port joining 、 inside structure of every module, etc. in detail. using hardware description language to program for function implementation, after function simulation 、 synthesis 、 place and route 、 timing simulation and download, the design is implemented in the spartan 3 serial xc3s400 - 4pq208 chips of xilinx. all procedure of design is worked under the ise 6. 2 integrated environment

    接著詳細分析了各模塊的功能、埠連接、內部結構等，並利用硬體描述語言編寫源代碼實現各模塊功能，經過功能模擬、綜合、布局布線、時序模擬、下載等一系列步驟，最終在xilinx的spartan3系列xc3s400 - 4pq208晶元上實現。
  16. At the same time, the main points in the design are outlined. the project can send the standard device requests, receive standard configuration descriptor and transmit data etc. waveform simula tion and time analysis are finished on maxplus ii

    本設計可以對主機發送的標準設備請求，返回設備描述符、傳送數據等操作，並在maxplus環境下進行了波形模擬和時序分析，時序模擬滿足設計要求。
  17. Finally, the text validates the control function of the fpga - based bottom control system trough the time simulation and the pd closed loop experiment

    最後，本文通過時序模擬和pd閉環實驗驗證了基於fpga的底層控制系統的控制功能。
  18. At last, it gives the corresponding functional simulation result and timing simulation result

    最後給出了相應的功能模擬和時序模擬結果。
  19. The vxibus c - size and i, q channels are employed in this module design, and the sampling rate in each channel reaches 500mhz. the memoty deep of the system is 2mb each channel and cpu is high - speed embedded cpu ( powerpc ). the timing and logic function are fulfilled by fpga. after the disscusion of signal adjusted, the detailed scheme of this module design have been showed. in this design, there is much logic function design, and it is very strict with the hardware language program. so the basic flow of hardware program design and several very important methods of high speed logic function design, which is described by vhdl, are introduced. also, expatiated the inner modules structure of fpga for forepart circuit, the keystone and difficulties of the design. the design of high - speed pcb is another difficuty of realizing high - speed data acquisition system, and it is very important. the timing simulating results of several pivotal modules are depicted. high - speed signal paths are terminated to match the characteristic impedance. the design undergoes integrity analysis and software simulation

    在本模塊的設計中，有著大量的邏輯設計，對硬體語言程序的編寫要求比較高，因此，文中介紹了硬體程序設計的基本流程，以及幾種基於vhdl硬體語言設計在高速邏輯設計中非常重要的方法。同時闡述了本模塊設計的前端fpga的內部模塊結構，設計的重點、難點，並給出了重要模塊的時序模擬結果。高速pcb的設計也是目前實現高速數據採集系統的難點和重點，文中詳細的闡明了高速pcb設計中的注意點，以及作者在設計本模塊時的經驗和心得。
  20. This is one kind project of hardware multiplexer based on the high - performance system on a programmable chip ( sopc ). in the project author integrate with the software and the hardware on a field programmable gate array ( fpga ), not only simplifying the overall system design, moreover realizing stably, high speed, low cost multiplexer ’ s design. the dissertation carry on three verification step that include function verification 、 time verification and prototype verification to guarantee each ip can work normally to satisfy the system performance requirement. then author introduce the realization of the multiplexer in detail, as well as the test and the debugging questions met in practice and solution of the questions

    本方案是一種基於可編程片上系統（ sopc ）的硬體復用器設計方案，其特點是將系統的軟體和硬體集成在一款現場可編程門陣列（ fpga ）上，使用該方案不但簡化了整個系統，而且實現了穩定、高速、低成本的復用器設計。對系統中各個功能模塊的整合和驗證採用功能模擬、時序模擬、原型驗證三個步驟進行，保證系統中各個功能模塊可以正常工作，並滿足系統的性能要求。然後詳細介紹了復用器的實現，以及測試和調試中遇到的問題及解決方法。
分享友人
分享到 Line

分享到臉書