時延電路 的英文怎麼說

中文拼音 [shíyándiànlù]
時延電路 英文
time delay circuit
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 電路 : [訊] circuit （ckt）; electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...
  1. The method of connecting timing into 1ogic i s explained in waveform po1ynomia1 on the basis of waveform concept in boo1ean process theory. and an ana1ytica1 de1ay mode1 that is close to practice circuits is found

    並在布爾過程論中定義波形的基礎上，說明了邏輯與時序在波形多項式中的結合方法，建立了接近實際電路的解析延遲模型。
  2. They are widely used in many fields such as telecommunications, finance, traffic, gymnasium etc. led drivers are necessary in the application of led displays. they can supply constant output current and make the led light even, and also can make the led ’ s life longer

    Led顯示屏的應用離不開它所需要的驅動控制電路，通過驅動電路來獲得良好而平穩的電流，使led顯示更加均勻，滿足各種場合的應用要求，同時可以延長led的使用壽命。
  3. According to the mean message traversal, the performance of leo / meo mobile satellite communication networks with intersatellite links ( isls ) is analyzed in this paper. three different traffic patterns are used in the analysis. if the isl number per satellite increases, the advantage of packet switch is more significant than that of circuit switch

    本文提出了一種基於信息平均傳輸距離的中/低軌衛星移動通信系統星際鏈路網路性能的分析方法.根據三種不同的業務分佈模型對繁/簡兩種網路的信息過網時延和呼叫丟失率進行了分析.通過增加網路中每個節點星際鏈路的數目可以改善網路的性能，而且這種改善對採用分組交換的系統比採用電路交換的系統大
  4. The clock recovery block of usb2. 0 transceiver macrocell consists of phase locked circuit, such as pll and dll ( delay locked loop ). this block use external crystal 12mhz sin signal to produce 60mhz, 120mhz, 480mhz clock signal, and can recover colock signal form date wave. it can support 480mbps ( hs ) and 12mbps ( fs ) word speeds as defined in usb2. 0 specification.

    目的是用鎖相環電路? pll和dll （延遲鎖相環）實現usb2 . 0收發器宏單元utm的時鐘恢復模塊。其中pll環路構成的時鐘發生器將外部晶振的12mhz正弦信號生成60mhz 、 120mhz 、 480mhz等本地時鐘信號。 dll環路依據本地時鐘信號對外部數據信號進行時鐘恢復。
  5. Abstract : a new clock - driven eco placement algorithm is presented for standard - cell layout design based on the table - lookup delay model. it considers useful clock skew information in the placement stage. it also modifies the positions of cells locally to make better preparation for the clock routing. experimental results show that with little influence to other circuit performance, the algorithm can improve permissible skew range distribution evidently

    文摘:提出了一種新的時鐘性能驅動的增量式布局演算法，它針對目前工業界較為流行的標準單元布局，應用查找表模型來計算延遲.由於在布局階段較早地考慮到時鐘信息，可以通過調整單元位置，更有利於后續的有用偏差時鐘布線和偏差優化問題.來自於工業界的測試用例結果表明，該演算法可以有效地改善合理偏差范圍的分佈，而對電路的其它性能影響很小
  6. As the key block of the wireless communication transmitter in rf, it is very useful in improving the output power and efficiency, lowering the loss of the supply, lowering the size and the weight, lengthening the time of communication. class e power amplifier which is suitable to amplify envelop signal is very important in modern communication system

    功率放大器（ pa ）作為無線通信射頻發射機中不可缺少的關鍵電路，對于提高手機的功率效率、降低電源損耗、減小體積重量、延長通話時間有著舉足輕重的作用，而適用於恆包絡信號放大的e類功率放大器，更是在現代通信系統中佔有十分重要的地位。
  7. Direct connect vias conduct so much heat away from the pin and into the plane that high temperature or long soldering time may be required to complete the joint - thermal damage could occur to both the board and the component from soldering or desoldering

    在焊接時，直接連接的過孔會通過引腳把大量的熱傳導至內電層，因此完成焊接就需要很高的溫度或者延長焊接時間，這就會導致在焊接或拆焊時發生電路板或元件的損壞。
  8. Reduce the load of access controller lower potential trouble nc no output, control all kinds of electric locks delay control circuit unlock delay time in 0 10s auto protection dimension : 180x77x77mm weight : 1410g

    設nc no輸出，可控制各種類型的電鎖。設延時控制電路，開鎖時間可在0 - 10秒。
  9. The technology of alternating - current - boosting by way of constant current is successfully used to charge capacitors with 25 kilojoules of energy in only eight seconds. rail - gap switch with performances of long life and highly steady state are designed. and the high voltage pulse generator, which can produce low - excursion and fast - rise pulses, are designed by using double trigger circuit and hydro - thyristor as switch

    在大功率恆流充電技術上，成功的應用了交流調壓式恆流技術，可以在8s內讓電容器儲存25kj的能量;設計出了長壽命、高穩定的軌道開關;採用氫閘流管做開關，使用雙觸發電路，研製出了低抖動、快前沿的高壓脈沖發生器（點火機） ;採用單片機和pld ，研製出了精度為10ns的延時同步機。
  10. The influence of the multi - layer cabling structure in integrated circuit on the signal delay

    大規模集成電路多層布線結構對信號延時的影響
  11. With the three - dimensional ray - tracing program, the simulation of leo - gps occultation is given. the radio path of occultation observation is simulated, and then the excess phase delay is calculated. this work can be used for studying the effects of the neutral atmosphere and ionosphere on the occultation observations and evaluating the performance of the inversion techniques

    本文介紹了無線電掩星技術的發展狀況和基本原理，圍繞無線電掩星技術及其應用研究展開諸多研究和探討，主要工作內容如下: 1 、利用全球三維射線追蹤程序，開展leo - gps掩星觀測的模擬研究，以計算掩星觀測時電波傳播路徑、計算大氣引起的附加相位時延等。
  12. Experimental results in this paper show our approaches can be efficiently used in delay testing for complex circuits with noise effects

    實驗表明，本文的方法可以應用在復雜超深亞微米電路的延時故障測試中，有一定推廣價值。
  13. Traditional static crosstalk identification methods identify crosstalk targets only using coupling capacitance and noise amplitude information, which lead to the pessimistic results and induce a long time to ic design convergence

    摘要傳統的靜態串擾噪聲識別演算法只驗證耦合電容和噪聲幅值信息，沒有考慮噪聲寬度對電路邏輯功能的影響，所以給出的結果過于保守，導致設計收斂的時間被延長。
  14. Analyze item by item the position of unintact cycle, the running clearance of unintact cycle, locking - deform, datum dimension regulating, repeatly install, power voltage wave and marking running etc. at the same time, we give the calculating formula to calculating the running marking random error, and use it to calculate the system error of big diameter measure instrument - - datum dimension frame error, gyro - wheel diameter error, error caused by circumstance temperature, error caused by backing distance, angle error, delay error of data collecting circuit, lathe main shaft running error, workpiece install partial error

    對不完整圓的位置、不完整圓的轉動間隙、鎖緊變形、基準尺調整、重復安裝、電源電壓波動、標記轉動等隨機誤差進行了逐項分析，並給出轉動標記隨機誤差的計算公式。對大直徑測量儀的系統誤差?基準尺尺架誤差、滾輪直徑誤差、環境溫度引起的誤差、後退距離引起的誤差、角度誤差、數據採集電路延時誤差、車床主軸回轉誤差、工件安裝偏心誤差分別進行了計算，最後對誤差進行合成。
  15. The use of time delays on these vehicles helps to eliminate transmission and motor damage by providing even and controlled acceleration. the delay is adjustable between 0 to 5 seconds and can be wired independently of other delays or alternatively these delays can be wired in cascade so that it is necessary for the first delay to switch on before the following commences timing etc. suppression is included in the delay circuit to prevent damage by voltage transients

    延遲開關可以調整延遲時間0 ~ 5秒，並可連接數個延遲開關來逐步控制連續動作之時間（復數連接時，第一個開關要啟動接下來的開關才會跟著動作）避免電動車起動初期之電力脈沖，達到平順的起步動作，可預防電壓無端變動造成之電路故障
  16. After analyzing and comparing different partition rules, md32 pipeline architecture is finally defined, which meets the required instruction function, frequency and timing spec of md32. a complete set of creative design method for risc / dsp md32 micro - architecture is presented, such as parallel design, internal pipeline, central control, etc. thanks to the adoption of these design methodology, control path and data path are separated, circuit delay is reduced, and complex instruction operations are balanced among multiple pipeline stages

    它們將若干復雜指令操作均勻分配在幾個流水節拍內完成，實現了任意窗口尋址等復雜指令操作，將整個處理器的數據通路與控制通路分離，減小了電路時延，從而滿足了risc dsp不同指令功能和系統時鐘頻率的要求，構成了統一的、緊密聯系的、協調的md32系統結構。
  17. The scheme takes advantages of repeaters and low - swing differential - signaling circuits on driving long wires in different length, and optimally inserts them along the wire in order to decrease delay and power of interconnects

    該方法利用中繼驅動器和低擺幅差分信號電路在驅動不同長度連線時的優點，將它們混合插入到連線的合適位置，從而降低互連的延時和功耗。
  18. So we can simultaneously simulate logic functions and delay properties of digital circuits really by description and computing methods that are based on boole process

    因此使用boole過程的描述和計算方法能夠更真實地同時對電路的邏輯功能和延遲特性進行模擬。
  19. Zero - delayed clock buffers are adopted in clock circuit so that it can meet the various clocks ’ requirement needed by the system

    時鐘電路採用零延時的時鐘buffer ，能很好的滿足各種時鐘的同源/同相要求。
  20. And software method can resolve d channel ' s work for its less data communication ; 3 ) cpu 80c152 is synchronized with mc145572 by a simple synchronous circuit, avoiding the complex fpga interface circuit ; 4 ) data transmission use dma, which reduces the delay of data transmission and cpu occupying ; 5 ) 8bit software look - up table method can achieve 16bit crc quickly, which reduces the resource of both hardware and software

    對通信數據量相對小的d通道，採用軟體實現裝幀與解幀。第三，採用結構簡單的外部同步時鐘電路實現80c152和接入晶元mc145572的同步傳輸，巧妙地避開了復雜的fpga介面電路。第四，利用dma技術完成數據快速收發，降低了數據傳輸時延及cpu佔用率。
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