時鐘信號 的英文怎麼說

中文拼音 [shízhōngxìnháo]
時鐘信號 英文
clock signal時鐘信號發生器 clock-signal generator
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 號 : 號Ⅰ名1 （名稱） name 2 （別號; 字） assumed name; alternative name3 （商店） business house 4 （...
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  1. To eliminate the bootless power dissipation of the redundant transition of the clock, a design method named det ( double - edge - triggered ) shift register is proposed

    摘要從消除時鐘信號冗餘跳變而致的無效功耗的要求出發，提出雙邊沿移位寄存器的設計思想。
  2. Then, we propose a design method named det ( double - edge - triggered ) shift register to eliminate the bootless power dissipation of the redundant transition of the clock

    接著，從消除時鐘信號冗餘跳變而致的無效功耗的要求出發，提出雙邊沿移位寄存器的設計思想。
  3. The tft lcm driver signals were enable signal and fiducial clock signal, which were strict with synchronization

    驅動信號主要為使能信號和基準時鐘信號，並要求二者具有嚴格的同步性。
  4. A clock signal with 1 million pulses per second is referred to as a 1 megahertz.

    每秒鐘有一百萬個脈沖及時鐘信號，也稱兆赫（）時鐘信號。
  5. A clock signal with 1 million pulses per second is referred to as a 1 megahertz

    每秒鐘有一百萬個脈沖及時鐘信號，也稱兆赫（ ? ）時鐘信號。
  6. The speed with which your microcomputer executes programs will vary linearly with the speed of your clock signal.

    你的微型計算機執行程序的速度將與你的時鐘信號的速度成線性關系。
  7. Clock recovery is an important and difficult part of tdm access, so the thesis will emphasize on it. and two methods of clock recovery are proposed in the thesis

    然後，本文對同步時鐘統計恢復法進行了分析，推導出了時鐘信號低頻抖動的時域和頻域特性公式，並利用matlab對低頻特性進行了模擬分析。
  8. The clock recovery block of usb2. 0 transceiver macrocell consists of phase locked circuit, such as pll and dll ( delay locked loop ). this block use external crystal 12mhz sin signal to produce 60mhz, 120mhz, 480mhz clock signal, and can recover colock signal form date wave. it can support 480mbps ( hs ) and 12mbps ( fs ) word speeds as defined in usb2. 0 specification.

    目的是用鎖相環電路? pll和dll （延遲鎖相環）實現usb2 . 0收發器宏單元utm的時鐘恢復模塊。其中pll環路構成的時鐘發生器將外部晶振的12mhz正弦信號生成60mhz 、 120mhz 、 480mhz等本地時鐘信號。 dll環路依據本地時鐘信號對外部數據信號進行時鐘恢復。
  9. The main research contents of this dissertation are shown in the following : ( 1 ) introduce one method of use the counting pulse to develop ie measuring system and new method of using the high frequency clock signal to divide the space pulse

    本文主要研究內容如下: （ 1 ）系統論述了一個脈沖計數方式的ie測量系統的測量原理，闡述了一個採用高頻的時鐘信號細分空間脈沖的新型細分方法。
  10. Above all, [ 12 : 8 ] harming error correction theory is mentioned in this paper. the edac circuit designed by vhdl can works normally at different frequency of the cpu clock such as 66mhz 50mhz 40mhz 33mhz. the edac function of the circuit can also be disabled by software tool. meanwhile, some basic devices such as and logic, or logic, not logic and some small scale integrated circuits are also integrated in the fpga

    本論文闡述了12 ， 8漢明碼糾錯設計過程，採用vhdl語言實現糾錯編碼器（ edac ） ，本設計能夠適應cpu時鐘信號clk2的不同頻率，如66mhz 、 50mhz 、 40mhz 、 33mhz ，並且能夠通過軟體的控制使fpga的糾錯編碼功能關閉。
  11. The level adjustment circuit 100 lowers the clock signal input to the first clock terminal ck1 by a predetermined value from h level and provides the signal to the gate of the transistor q5

    電平調節電路100將送往第一個時鐘終端ck1的時鐘信號從h電平降低一個預定值，並將此信號送往晶體管q5的輸入端。
  12. Oscillator generated a wave with frequency 132 khz as the clock signal

    振蕩器電路產生一個頻率在132khz附近抖動的矩形波作為整個電路的時鐘信號。
  13. The transition from voltage to no voltage is referred to as the trailing edge of a clock signal.

    電感從一定值下降到0值的躍遷叫做時鐘信號的后沿。
  14. The device always generates the clock signal

    時鐘信號總是由設備端生成的。
  15. Supports external wait signal to expend the bus cycle

    支持外部等待時鐘信號延長總線周期。
  16. Controllable rsfq timing pulse generator

    可控時鐘信號發生器
  17. Real - time power angle measurement of a synchronous generator based on gps clock signal and tachometer

    時鐘信號的發電機功角實時測量方法
  18. Traces on opposite sides of the board should run at right angles to each other

    快速切換的信號，例如時鐘信號，應該用地線屏蔽，以避免將噪聲輻射到其他部分。
  19. The third, the whole circuit of digital cmos image sensor is presented. the circuits of pixel array, clock signal generator and sam have been improved on the base of simulation

    再次，我們對整個cmos數字圖像傳感器進行了電路設計，主要包括：時鐘信號發生器，順序移位寄存器和像素陣列。
  20. The following is main content of our thesis. the first, we analyze the system operation theory of cmos image sensor with pixel level adc ( a / d converter ). it is made up of three sections : pixel array, clock signal generator and sam ( sequential access memory )

    本文的主要內容如下：首先，我們對像素級a d轉換型圖像傳感器的系統工作原理進行了分析，是由像素陣列、時鐘信號產生器和sam （順序讀寫存儲器）三部分構成的。
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