時鐘時序電路 的英文怎麼說

中文拼音 [shízhōngshíxùdiànlù]
時鐘時序電路 英文
clocked sequential circuit
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  • 時序 : [地質學] sequence; sequential; time sequence; timing sequence; sequence in time
  • 電路 : [訊] circuit （ckt）; electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...
  1. The sy - stem had different requirements on time sequence in high - speed clock and low - speed clock situations, which resulted in the complexity of the sequential circuit

    在高速時鐘和低速時鐘的情況下，系統有不同的時序要求，這就決定了時序電路的復雜性。
  2. Conditional sensitization of paths is presented from the sensitization theorem of sequential circuits and a novel exact clocking method based on single - period sensitization is proposed. compared with tranditional methods, it is not too optimistic or pessimistic, fit for the exact timing of high - speed circuit design

    在時序邏輯電路精確定時方面，從時序電路的敏化定理出發，使用本文給出的條件可敏化概念，通過對通路敏化性質的判斷建立了一種新的單周期敏化的時序電路最小時鐘周期精確確定方法。
  3. The third, the whole circuit of digital cmos image sensor is presented. the circuits of pixel array, clock signal generator and sam have been improved on the base of simulation

    再次，我們對整個cmos數字圖像傳感器進行了電路設計，主要包括：時鐘信號發生器，順序移位寄存器和像素陣列。
  4. According to the request of this subject, we have developed the system hardware and software for the slave device and the inspection software running on the pc. in this paper all of the followings is illustrated detailedly, such as the research on the principles of measurement and its realization, three means of water - level measurement that are separately based on photo electricity coder, pressure sensor and potentiometer ; selection of the microchip, we choose an advanced integrated soc ( system on chip ) microchip c8051f021 as the main controller ; realization of signal sampling, processing and its conversion in the mcu ; application of high precision 16 bits adc cmos chip - - ad7705 in our system, designing its interface with the microchip and relevant program ; using a trickle charge timekeeping chip ds1302 in the system which can provide time norm and designing of its i / o interface and program ; additionally, a 4 ~ 20ma current output channel to provide system check - up using ad421. in the system, ad421, ad7705 and the microchip compose spi bus ; to communicate with the master pc, here we use two ways which are separately rs232 and rs485 ; moreover, there are alarm unit, keyboard unit, power supply inspection unit and voltage norm providing unit in the system

    針對研製任務的要求，課題期間研製了下位機系統硬體和軟體，開發了上位機監控軟體，其中所作的具體工作包括：測量原理的研究和在系統中的實現，在本次設計中用三種方法來進行水位測量，分別是旋轉編碼器法、液位壓力傳感器法和可變電阻器法；主控晶元的選擇，我們選用了高集成度的混合信號系統級晶元c8051f021 ；實現了信號的採集和處理，包括信號的轉換和在單片機內的運算；高集成度16位模數轉換晶元ad7705在系統中的應用，我們完成了它與單片機的介面設計及程序編制任務；精確時鐘晶元ds1302在系統中的應用，在此，我們實現了用單片機的i o口與ds1302的連接和在軟體中對時序的模擬，該晶元的應用給整臺儀器提供了時間基準，方便了儀器的使用；另外，針對研製任務的要求，還給系統加上了一路4 20ma模擬信號電流環的輸出電路來提供系統監測，該部分的實現是通過採用ad421晶元來完成的，本設計中完成了ad421與單片機的spi介面任務，協調了它與ad7705晶元和單片機共同構成的spi總線系統的關系，並完成了程序設計；與上位機的通信介面設計，該部分通過兩種方法實現： rs232通信方式和rs485通信方式；系統設計方面還包括報警電路設計、操作鍵盤設計、電源監控電路設計、電壓基準電路的設計。
  5. The article also includes the work as follows : 1. finished designing the hardware collective circuit and its controlling program, and using the dissynchronous fifo technique and independent clock circuit to solve the problem of high - accuracy regular - frequency sampling and the match system speed

    論文還完成了以下工作： 1設計現場診斷儀的硬體採集電路及相應控製程序。應用異步fifo技術和獨立時鐘電路，解決了高精度定頻率采樣以及系統速度匹配問題。
  6. Finally the timing problems in high - speed circuit design were analyzed and the conditions of timing design in source synchronous clock system were derived

    最後分析了高速電路設計中時序問題，給出了源同步時鐘系統中時序設計應該滿足的條件。
  7. According to elaborate analysis of clock logic in general purpose processor, we apply multi - bit clock gated flip - flops design to reduce the power of registers and clock trees concurrently, so the power of the clock network in processors can be drastically reduced. 3. a low power issue queue architecture is proposed

    一方面利用帶門控使能的觸發器電路降低時鐘節點的平均翻轉，另一方面通過多比特觸發器的採用進一步降低了時鐘樹規模，從而在不增加asic物理設計復雜度的情況下大大降低了龍芯處理器的時鐘網路功耗; 3 .提出了亂序多發射隊列的低功耗結構。
  8. However in soc or high performance cpu an in - chip high quality clock is required to guarantee the timing of all chips

    而soc或者高端的cpu一般都採用同步的數字電路設計，時鐘是整個晶元時序的保證。
  9. For examp1e, the sort arithmetic so1ves 1eve1 partition of combination 1ogic ; the computing input waveform of sensitized path makes the possib1e of conf1rm the minimum c1ock circ1e ; the cyc1e - - based method for synchronous op tajg1fyjct7 : @ + $ { 4it x sequentia1 circuits improve the speed of waveform simu1at ion

    其中，編排級數法確定了組合邏輯的層次關系；通路敏化輸入波形方法決定了最小時鐘周期；基於周期的同步時序電路的模擬演算法加快了模擬的速度等。
  10. According to the redundancy in digital circuits, we investigate the diversified redundancy - restraining techniques for lower - power cmos circuits. to erase the redundant transition of the clock, the logic design of double - edge - triggered flip - flop is presented and applied in sequential circuit design

    為消除時鐘信號的兀余跳變，提出了利用時鐘兩個方向跳變的雙邊沿觸發器邏輯發計並應用於時序電路設計中。
  11. In this system, high speed clock is produced by the clock circuit when acquiring and feeding back signal. the required clock is produced by the pc program when communicating

    在本系統中採集和回放時所需的高速時鐘由時鐘電路產生，通訊時所需的時鐘則由上位機的程序產生。
  12. Through clock circuit of hardware and device driver program of software, this paper realizes real - time cortrol, moreover, by making use of event synchrocyclotron mechanism, resolves the interrupt problem

    摘要運用硬體上的時鐘電路和軟體上的設備驅動程序實現了實時控制，並採用事件同步機制解決了中斷問題。
  13. The thesis includes the design of hard circuit, pcb ( printed circuit board ), driver and application soft involving a / d board and d / a board. the detailed functional modules consist of multiplex signals select module 、 analog digital conversion module 、 digital analog conversion module 、 pci protocol conversion module 、 driver and magnifying module 、 control logic 、 clock circuit and configuration circuit. the importance of the thesis is a / d board

    本課題包括硬體電路、印刷電路板（ pcb ） 、驅動程序和應用軟體的設計，涉及a / d板和d / a板兩大塊部分，具體的功能模塊包括多路信號選擇模塊、模數轉換模塊、數模轉換模塊、 pci協議轉換模塊、驅動放大模塊、控制邏輯、時鐘電路和配置電路，其中重點是a / d板部分。
  14. To avoid the idleness state and the corresponding power dissipation in sequential circuits, a clock gating technique and a multi - code assignment using redundant state is adanced to reduce power dissipation

    為抑制時序電路中的冗餘現象，研究了時序電路的門控時鐘技術，並利用t型觸發器進行時序電路設計。
分享友人
分享到 Line

分享到臉書