晶元互連 的英文怎麼說
中文拼音 [jīngyuánhùlián]
晶元互連
英文
chiinterconnection-
Applying two perpendicular polarized light states and a no - light state to express information, this new theoretical system covers : a ) whole architecture constructed from light processing, light transmission, electric control and photoelectric input and output ; b ) various computing units mainly consist of liquid crystal element and polarimeter ; c ) light bus mainly consists of interlinkage optic valves ; d ) ternary memory formed from semiconductor memory ; e ) register formed from optic fiber ring ; and i ) huge - numeral management based on the new concept of calculating path and calculating channel
這個理論包括：光處理、光傳送、電控制、綜合輸入輸出的總體結構；以液晶元件和偏振器為主的各類運算器結構；以互連光閥為主的光空間總線；以半導體存儲器為主的三值數據存儲器結構；以光纖環為主的寄存器結構；以算位、算道新概念為基礎的巨位數管理方案等。Now that a single chip is an entire system ( the concept of system - on - a - chip, soc ), on - chip interconnect is now one of the most challenging areas of 1c processing
隨著系統晶元的出現，片內互連技術已成為目前集成電路設計中最具挑戰性的領域之一。Integrated circuit design has entered into the era of system on chip ( soc ), the bus interconnect architecture of system on board have also developed into a kind of hierarchy architecture - on chip bus ( ocb )
隨著集成電路設計進入到系統晶元（ soc ）時代，板極系統的總線互連結構也發展成為系統晶元的層次化總線體系一片上總線。When the silicon technology comes to deep sub - micron level, the interconnect delay exceeds the gate delay ; and because of the increase of 1c work frequency, the allowable errors become smaller, and the influence of the transmission delay gets bigger, which increase the difficulty of the circuit design
在深亞微米製造技術中，晶元互連線延遲超過門延遲，而且隨著集成電路工作頻率的提高，允許的時序容差變小，傳輸延遲的影響加大，設計工作難度增加。The “ personality ” of the chip ( its logical functions and interconnections ) can be changed dynamically in nanoseconds merely by changing its configuration bits
只要讓組態位元發生變化，晶片的性格（也就是它的邏輯功能與相互連結）也會動態地跟著在奈秒之間發生改變。In the course of design, we fully consider the actual conditions on the railway and take a series of corresponding measures to the concrete problem. such as we select high - accuracy microconvertor and have the converted function in succession data collecting system chip aduc812, design v / f circuit and external a / d circuit. in anti - interference of the hardware, we try to disperse each function module to avoid interfering each other, adopt photoelectric isolated technology to dispel the circuit connection of input and output. in controlling we import arithmetic mean into strain wave algorithm and real computing technology of virtual value for sample treatment of data, that is using the software to smooth away interfere error and to calculate actual value, thus it makes the precision of the data improve greatly
在設計過程中，根據系統要求，充分考慮鐵路上的實際情況，針對具體問題採取了一系列的相應措施，如在器件選擇方面選用高精度microconvertor系列、具有adcdma連續轉換功能的數據採集微控制器晶元aduc812 ，設計了v f變換電路和外部a d轉換電路；在硬體抗干擾方面，將每個功能模塊盡量分散獨立開來以避免相互干擾、採用光電隔離技術消除輸入輸出通道上的電路聯系；在控制方面對于采樣數據的處理引入了算術平均值濾波演算法和真有效值的計算方法，即通過使用軟體來濾除系統中有干擾造成的誤差並計算真值，從而使數據的準確性得到極大地提高。It was found that the interfacial bonding of 93w - ofc was both the joining action of ofc / w grains and that of ofc / ni - fe binders, whereas the joining of ofc to tc4 could be seen as the mutual intense diffusion effect between ofc / tc4 and as a result cu - ti intermetallic compounds were formed at the joint. the joining of tc4 - a1 and a1 - mb2 were also attributed to the result of diffusion between elements ti - al and al - mg respectively. on the other hand, residual thermal stress and stress - induced distortion were produced at the joint simultaneously due to the difference in thermal expansion coefficient of different welding " materials
研究表明， 93w與ofc的界面連接是ofc與93w中w晶粒的連接以及ofc與93w中ni - fe粘接劑的連接共同作用的結果； ofc與tc _ 4連接界面的形成是由於ofc與tc _ 4之間發生反應擴散，並由此在二者接頭處生成了cu - ti金屬間化合物的中間相； tc _ 4 - al的連接與al - mb _ 2的連接則分別是其基體元素ti 、 al之間和al 、 mg之間元素互擴散的結果，另外，由於熱膨脹系數的差異，擴散焊接后在不同焊件的接頭處存在殘余熱應力並由此引起接頭的形變。A bus shared heterogeneous architecture consisting of one or more instruction set processor cores, one or more dedicated hardware ip cores and one or more on - chip memories usually provides a good solution
基於總線互連的由一個或多個指令集處理器核、一個或多個專用硬體ip核、一片或多片片上存儲器構成的異質體系結構成為媒體系統晶元的合理選擇。After analyzing the characteristic of the parallel processing system, some problems about design missile - carrying processing system are pointed out ; network in the parallel processing system has become bottleneck and affect the performance of system, so the processing efficiency is analyzed in a multiprocessor system based on cluster - bus and some rules in designing the network in the multiprocessor system are brought out ; genetic algorithm is used for scheduling in the multiprocessor system, and a scheduling algorithm is described to suit arbitrary number of tasks, unequal task processing time, arbitrary precedence relation among tasks and arbitrary number of parallel processor, so that the schedule length will be minimized ; finally, an atr algorithm is mapped to a ring multiprocessor system, and a block diagram using dsp device is constructed. in chapter 4, the study is performed on real - time system hardware realization of atr. tms320c80 is selected as the kernel processor in multiprocessor system
為此，對一種由常用的dsp晶元組成的多處理器系統的處理器利用率進行了分析，提出了多處理器系統互連網路設計的基本原則；本章使用遺傳演算法作為實現多處理器調度的工具，提出了一種新的任務調度演算法，該演算法主要是為了解決在任務數任意、任務計算時間不相等、任務前趨關系任意、以及任務間存在通信和考慮任務存貯器要求的情況下，如何優化任務在各個處理器上的分配和執行順序，使得多處理器系統總的執行時間最小；最後對一個目標識別演算法進行了硬體實現優化分析，根據分析結果，將演算法映射到由dsp晶元組成的環形網路連接的處理器拓撲結構上，得到了多處理器系統的原理框圖。For the image acquisition of optical scan mode, normally, ccd image sensor is used to capture image, but in our system, due to the system request of micromation and high integration, cmos image sensor is adopted as the image collection device, and then the thesis gives a interface circuit between the chip and dsp and a control solution of image collection ; toward the information storage in our solution, dsp is directly linked to usb host chip and it is the dsp that accomplishes the processing of usb protocol and interface control so as to reduce the cost, minimize product cubage and consequently meet the requirement of system micromation ; at the same time, the thesis probes preliminarily into usb otg ( on - the - go ) technology, which offers an approach between embedded machines including pda, mobile phone, printer, digital camera and so on ; in addition, some attempts on the other application area with tms320vc5402 which was commonly used to voice processing and static image processing are done, for example, to arrange the chip to control lcd module directly
在圖像的光電掃描輸入上，傳統方案大部分採用ccd型圖像傳感器，而在本方案中，根據系統微型化、高集成的特點，使用了cmos圖像傳感器作為攝像器件，並且設計了該晶元與dsp的一種介面電路以及圖像採集控制方案；在信息存儲上，本方案採用dsp直接與usbhost晶元連接，由dsp處理usb協議和介面信息，從而降低了系統成本、縮小了產品體積，滿足了系統微型化的要求；同時本論文也對usb - otg技術進行了初步探討，利用此項技術，不再需要計算機作為主機，就能實現在pda 、移動電話、印表機、數碼相機等嵌入式應用之間直接互聯通信；另外也對廣泛用於語音處理和靜態圖像處理的tms320vc5402其它方面的應用進行了嘗試，比如直接控制液晶顯示器等。An idea is brought forth to design the total structure of the usb interface ip, the main control logic, the mcu interface ( the function is the same as the pdiusbd12 chip of the philips semiconductor ) and a dpll which is used to synchronize data and separate the clock. this paper also introduces packet recognition, transaction sequencing, sop, eop, reset, resume signal detection / generation, nrzi data encoding / decoding and bit - stuffing, crc generation and checking ( token and data ), packet id ( pid ) generation and checking / decoding,
提出設計了usb介面電路的整體構架，設計了usb的主要控制邏輯和與mcu的互連的介面（此介面與飛利普的usb介面晶元pdiusbd12兼容） ，也設計了一個數字鎖相環（ dpll ）來同步數據和分離時鐘，並對同步模式的識別、并行/串列轉換、位填充/解除填充、 crc校驗/產生、 pid校驗/產生、地址識別和握手評估/產生做了具體的分析。However, some improvements have been made for the distributed rc model, the precision ca n ' t attain the request due to the influence of parasitic effect especially the increasing inductance with the development of interconnect technologies in deep - submicrometer region. so these influences must be taken into consideration and the building of new distributed rlc model for interconnect delay and crosstalk becomes more importance. according to this model, two cases, that is, cmos driving transmission line and interconnect line between chips have been analyzed
對傳統的分佈rc模型進行了改善，但隨著互連向深亞微米級發展，寄生效應的影響尤其是電感的影響，必須考慮，因此建立新的rlc傳輸模型是很必要的，本文提出了這種新的互連模型，並對cmos驅動互連線和晶元之間互連兩種情況進行了分析，驗證了延時模型是可靠和精確的，並對延時的改善起到了指導作用。Wire bonding is the most classical and most mature technique for ic interconnection, which takes most of the market share, there are also a lot of research on ultra - fine - pitch wire interconnection must to do
摘要引線鍵合是應用時間最長、技術最為成熟且目前市場?有率最高的晶元連接技術，但應用於超細間距引線互連還有許多技術有待研究。Design verification problem needs hierarchy methodology. because the effect of interconnection has taken in the highest flight, design verification for the interconnection network, for example, only the completed verification for performance of power supply of p / g network can ensure the reliability of chip
由於晶元內互連線作用已佔相當重要的地位，在對互連線網路作精確的設計驗證，例如，晶元電源地網的供電性能的驗證，是晶元工作的可靠性的保證。分享友人