柵氧化物 的英文怎麼說
中文拼音 [zhàyǎnghuàwù]
柵氧化物
英文
gate oxide-
This voltage creates a field across the gate oxide, which causes the adjacent p substrate to invert to n-type.
這一電壓在柵極氧化物層上產生一個電場，它導致毗鄰的P型襯底轉變成N型。A new physical model of tddb of ultra - thin gate oxides is presented on the bases of above analysis
為超薄柵氧化層的經時擊穿建立了一個新的物理模型。Avalanche injection stacked gate mos
雪崩注入多層柵金屬氧化物半導體Plastic barrier, adopted hard upvc material, is a recycling high molecular compound being non - toxic, anti - ultraviolet radiation and anti - oxidation
塑膠柵欄選用硬質聚乙烯材質是一種無毒，抗紫外線，抗氧化且可回收利用的高分子化合物。Xing su ( microelectronics and solid state electronics ) directed by prof. lin chenlu the fast development of information technology requires integrated circuit to be greater integrated, faster functioned, and lower power - consumed, that lead to continuous shrinkage of mos and dram feature size. and under this trend the thickness of mos gate dielectrics ( sio2 ) would soon scale down to its physical limit
日益增長的信息技術對更高集成度、高速、低功耗集成電路的需求，驅使晶體管的尺寸越來越小，隨之而來的問題是作為mos柵氧化物和dram電容介質的sio _ 2迅速減薄，直逼其物理極限。V groove mos transistor
槽型柵金屬氧化物半導體晶體管The effect of a few important geometrical and physical parameters which include the length of the active region, the thickness of the active region, bulk traps, interface traps, on the tft ( thin film transistor ) characteristics of polycrystalline silicon has been investigated by using advanced two dimensional device simulation program medici
摘要利用高級二維器件模擬程序medici分析了多晶矽薄膜晶體管有源區的長度、體內陷阱、界面陷阱、柵氧化層厚度等幾何參數及物理參數，並研究了這些參數對薄膜晶體管特性的影響。V groove mos device
槽型柵金屬氧化物半導體掐This voltage creates a field across the gate oxide, which causes the adjacent p substrate to invert to n - type
這一電壓在柵極氧化物層上產生一個電場，它導致毗鄰的p型襯底轉變成n型。Since metal - oxide - semiconductor ( mos ) device appeared, integration of integrated circuit ( ic ) expands as moore law. meanwhile the dimension of device scales down, the thickness of sio2 gate dielectric shrinks as the same law. but as the thickness of sio2 gate dielectric reaches at isa, the gate current rises very quickly and reaches at 1 10a / cm2
自從金屬-氧化物-半導體（ mos ）器件出現以來，集成電路的集成度按照摩爾定律增加，相應地，器件的物理尺寸按照等比縮小的原則不斷縮小， sio _ 2作為柵介質的厚度不斷縮小，特徵尺寸在0 . 1 m以下的集成電路要求sio _ 2柵介質的厚度小於1 . 7nm 。分享友人