柵電壓 的英文怎麼說

中文拼音 [zhàdiànyā]
柵電壓 英文
gate voltage
  • 柵 : 柵名詞（柵欄） railings; paling; palisade; bars
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 壓 : 壓構詞成分。
  • 電壓 : voltage; electric tension; electric voltage
  1. Source of electron gun grid bias

    電子槍柵偏壓電源
  2. I designed a measuring system which can measure the anode current 、 anode voltage 、 grid current and grid voltage at one time. working at manual mode the system can sever as a measuring instrument

    根據要求，設計一個場發射參數的測量系統，此系統，工作在手動方式下可以測量出某一時刻點的場發射的陽極電流、陽極電壓、柵極電流、柵極電壓。
  3. This voltage creates a field across the gate oxide, which causes the adjacent p substrate to invert to n-type.

    這一電壓在柵極氧化物層上產生一個電場，它導致毗鄰的P型襯底轉變成N型。
  4. The factors limiting the frequency band of the wide - band amplifier are introduced. through analyzing the effects of the intrinsic parameters and parasitical on the frequency characteristics, a method of improving fr of mosfet by using short channel device and making mosfet work at the saturation region through raising vgs is put forward ; the effects of different kinds of circuit configurations on the frequency characteristics and the junction voltage on the voltage pattern circuit, current pattern circuit and frequency characteristics are analyzed. according to the linear theory of transconductance which is applied in the bit circuit, the current pattern amplifier circuit, current transfer circuit and output circuit which consist of mosfet and the wide - band amplifier composed of them are put forward

    介紹了限制寬帶放大器頻帶寬度的因素，通過分析mosfet的本徵參數、寄生參數對頻率特性的影響，提出了採用短溝器件、使mosfet工作在飽和區、抬高柵源電壓等提高mosfet特徵頻率的方法；分析了不同電路組態對放大器頻率特性的影響、節點電壓對電壓模電路、電流模電路頻率特性的不同影響，根據應用於雙極晶體管電路的跨導線性原理，提出了採用mosfet構成的電流模放大電路、電流傳輸電路、輸出電路以及由它們所組成的寬帶放大器，獲得了良好的頻率響應。
  5. A model of the interface state density distribution near by valence band is presented, and the dependence of the threshold voltage on temperature, the c - v characteristics and the subthreshold characteristics are predicted exactly with this model ; the effects of s / d series resistance on the output characteristics, transfer characteristics and effective mobility of sic pmosfets are analyzed. thirdly, the output characteristics and the drain breakdown characteristics are modeled with the procedure medici. the output characteristics in the room temperature and 300 ? are simulated, and the effects of gate voltage. contact resistance, interface state and other factors on sic pmos drain breakdown characteristics are analyzed

    提出了一個價帶附近的界面態分佈模型，用該模型較好地描述了sicpmos器件閾值電壓隨溫度的變化關系、 c - v特性曲線以及亞閾特性曲線；分析了源漏寄生電阻對sicpmos器件輸出特性、轉移特性以及有效遷移率的影響；論文中用模擬軟體medici模擬了sicpmos器件的輸出特性和漏擊穿特性，分別模擬了室溫下和300時sicpmos器件的輸出特性，分析了柵電壓、接觸電阻、界面態以及其他因素對sicpmos擊穿特性的影響。
  6. Charge pump circuits that make use of charge accumulation in the capacitor can pump charge upward to produce voltage higher than the regular supply voltage, and they are widely used in memory circuits, such as flash memory, for the programming and erasing of the floating - gate devices

    電荷泵是一種運用電荷在電容中的積累來產生高壓（高於電源電壓）的電路，它廣泛應用在存儲器電路中，諸如flashmemory ，用於對懸浮柵器件進行寫或擦除操作。
  7. By comparing and analyzing the advantages and disadvantages of three kinds of voltage reference circuits, type of current density ratio compensation 、 weak inversion type and type of poly gate work function, a cascode structure of type of current density ratio compensation is chosen to form the core of voltage reference circuit designed in this paper. applying the negative feedback technology, an output buffer and multiply by - 2 - circuits are designed, which improve the current driving capability

    然後通過比較和分析電流密度比補償型、弱反型工作型和多晶硅柵功函數差型三種帶隙電壓基準源電路結構的優缺點，確定了電流密度比補償型共源共柵結構作為本設計核心電路結構，運用負反饋技術設計了基準輸出緩沖電路、輸出電壓倍乘電路，改善了核心電路的帶負載能力和電流驅動能力。
  8. Based on the hydrodynamic energy transport model, the influence of variation of negative junction depth caused by concave depth on the characteristics of deep - sub - micron pmosfet has been studied. the results are explained by the interior physical mechanism and compared with that caused by the source / drain depth. research results indicate that with the increase of negative junction depth ( due to the increase of groove depth ), the threshold voltage increases, the sub - threshold characteristics and the drain current driving capability degrade, and the hot carrier immunity becomes better in deep - sub - micron pmosfet. the short - channel - effect suppression and hot - carrier - effect immunity are better, while the degradation of drain current driving ability is smaller than those with the increase of depth of negative junction caused by source / drain junction shallow. so the variation of concave depth is of great advantage to improve the characteristics of grooved - gate mosfet

    基於能量輸運模型對由凹槽深度改變引起的負結深的變化對深亞微米槽柵pmosfet性能的影響進行了分析，對所得結果從器件內部物理機制上進行了討論，最後與由漏源結深變化導致的負結深的改變對器件特性的影響進行了對比.研究結果表明隨著負結深（凹槽深度）的增大，槽柵器件的閾值電壓升高，亞閾斜率退化，漏極驅動能力減弱，器件短溝道效應的抑制更為有效，抗熱載流子性能的提高較大，且器件的漏極驅動能力的退化要比改變結深小.因此，改變槽深加大負結深更有利於器件性能的提高
  9. For the demand of output swing, the bias is provided by high - swing cascode current mirrors

    為了獲得高輸出擺幅，設計低壓共源共柵電流鏡為運放提供偏置。
  10. It shows that the bias in the post - irradiation recovery period and the ratio of the interface state to the electron tunneling influence the recovery rate

    模擬結果表明：退火過程所加柵偏壓的大小以及隧道電子效應與建立的界面態所佔比例的不同影響器件的恢復率。
  11. The low insertion loss is achieved by optimizing the transistor widths and bias voltages, by minimizing the substrate resistances, and by dc biasing the transmit and receive nodes, which decreases the capacitances while increasing the p1db

    通過優化mosfet的柵寬及偏置電壓可以降低插入損耗。在版圖設計中通過增加襯底接觸降低襯底電阻，從而減小插入損耗。另外，為接收和發送端提供直流偏置可以降低p1db 。
  12. In this paper, the theory of negatively charged surface states is used to investigate dynamic breakdown characteristics and the increase of gate - drain breakdown voltage as well as the reduction of saturated drain - source current after sulfur passivation. the measure which can improve the stability of sulfur passivation is proposed

    本論文通過對gaasmesfet擊穿機理和硫鈍化機理的研究，用負電荷表面態理論，解釋了gaasmesfet動態擊穿特性及硫鈍化后柵漏擊穿電壓增大、源漏飽和電流減小的機理，提出了改善硫鈍化穩定性的措施。
  13. The feedback of the output voltage is the major control loop. to achieve better frequency response and disturbance rejection of the input voltage, a input voltage feed - forward system is introduced in control loop. the duty - cycle of pwm applied at the gate of power mosfet is modulated by both input and output voltage

    該晶元採用的控制方式為電壓型pwm （脈沖寬度調制， pulsewidthmodulation ）控制方式，以輸出電壓反饋作為主要控制參量，同時為了提高晶元對輸入電壓擾動的響應速度，採用了輸入電壓前饋方法，將輸入電壓因素引入了反饋控制環中，通過對輸入輸出電壓的檢測，控制加在功率mos管柵極電壓上矩形脈沖的占空比，進而調節輸出電壓。
  14. Secondly, the radiation effects of the system of silicon gate si / sio2 ( silicon gate nmos and pmos ) implanted bf2 are made a deep systematic study. especially, the relationship between threshold voltage shift ( vth and vit vot ) in radiated mos transistor and irradiation dose rate, irradiation dose, irradiation temperature, bias voltage, device structure as well as annealing condition is explored emphatically

    在此基礎上，對bf _ 2 ~ +注入硅柵si sio _ 2系統低劑量率輻照效應進行了深入系統的研究，著重研究了bf _ 2 ~ -注入mos管閾值電壓漂移（ vth和vit 、 vot ）與輻照劑量率、輻照總劑量、輻照溫度、偏置電場、器件結構以及退火條件的依賴關系。
  15. We also studied some characteristics of sidagating effect using mesfet fabricated in planar boron implanted process including photosensitive, hysteresis, influence of sidegating effect on mesfet threshold voltage, influence of drain - source voltage on sidegating threshold voltage, influence of exchanging drain and source electrode on sidegating threshold voltage, relation between sidegating threshold voltage and the distance between side - gate and mesfet, relation between sidegating effect and floating gate, and so on

    本文還採用平面選擇離子注入隔離工藝，開展了旁柵效應的光敏特性、遲滯現象、旁柵效應對mesfet閾值電壓的影響、 mesfet漏源電壓對旁柵閾值電壓的影響、漏源交換對旁柵閾值電壓的影響、旁柵閾值電壓與旁柵距的關系、旁柵效應與浮柵的關系等研究。
  16. On the one hand, the design uses low voltage cascode op framework to improve its gain ; on the other hand, it applies self - bias and cascode structure to the whole sensing circuit. by using the improved method, we have successfully obtained low power consumption, low offset, high linear and high psrr ptat current generator under low power supply

    在電路設計上一方面改進運放結構，採用低壓共源共柵結構以提高其增益，另一方面整體傳感電路採用自偏置結構和共源共柵電流鏡結構，在低電源電壓下成功設計了低功耗、低失調、高線性度和高電源電壓抑制比的ptat電流產生電路。
  17. Abstract : a new approach, gate - capacitance - shift ( gcs ) approach, is described for compact modeling. this approach is piecewise for various physical effects and comprises the gate - bias - dependent nature of corrections in the nanoscale regime. additionally, an approximate - analytical solution to the quantum mechanical ( qm ) effects in polysilicon ( poly ) - gates is obtained based on the density gradient model. it is then combined with the gcs approach to develop a compact model for these effects. the model results tally well with numerical simulation. both the model results and simulation results indicate that the qm effects in poly - gates of nanoscale mosfets are non - negligible and have an opposite influence on the device characteristics as the poly - depletion ( pd ) effects do

    文摘:提出了一種新的建立集約模型的方法，即柵電容修正法.此方法考慮了新型效應對柵電壓的依賴關系，且可以對各種效應相對獨立地建模並分別嵌入模型中.另外，利用該方法和密度梯度模型建立了一個多晶區內量子效應的集約模型.該模型與數值模擬結果吻合.模型結果和模擬結果均表明，多晶區內的量子效應不可忽略，且它對器件特性的影響與多晶耗盡效應相反
  18. We can obtain the trap density by measuring the change of gate voltage of mos capacitance under constant current stress and the change of high frequency c - v curve before and after the stress

    該方法根據電荷陷落的動態平衡方程，測量恆流應力下mos電容的柵電壓變化曲線和應力前後的高頻cn曲線變化求解陷階密度。
  19. And the differernt characteristics of different close voltages are analyzed. at last, an experimental full bridge device is designed and some experiments are carried out. the results of the experiments show that the drive and protect circuit has excellent performances

    本文還對不同關柵電壓的關斷特性進行了分析，最後對所設計的驅動保護電路進行了實驗，結果令人滿意，證明所提出的驅動保護電路的可行性。
  20. The effects of the operation temperatures, gate voltages, drain - source voltages and magnetic field upon the characteristic of device are analyzed in detail. coulomb blockade and single electron tunneling are observed in the devices. 3

    詳細地分析了工作溫度、柵極電壓、漏源電壓和磁場對其特性的影響，觀測到明顯的庫侖阻塞效應和單電子隧穿效應，器件的工作溫度可達到77k以上。
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