模擬時鐘 的英文怎麼說

中文拼音 [mónǐshízhōng]
模擬時鐘 英文
simulation clock
  • 模 : 模名詞1. （模子） mould; pattern; matrix 2. （姓氏） a surname
  • 擬 : 動詞1. （設計; 起草） draw up; draft 2. （打算; 想要） intend; plan 3. （模仿） imitate
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 模擬 : imitate; simulate; analog; analogy; imitation; simulation模擬艙 boilerplate; 模擬電路 [電學] circ...
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  1. This reset their body clocks as if they ' d taken a six - hour plane trip to the east

    這樣可以模擬出向東飛行6小時，機體生物鐘的調整狀況。
  2. The three - order modulator has a 2 - 1 cascaded structure and 1 - bit quantizer at the end of each stage, the modulator is implemented with fully differential switched - capacitor circuits. and then, the discussion will begin by exploring the design of various circuit blocks in the modulator in more detail, i. e., ota, switched - capacitor integrator, quantizer, two - phase non - overlapping clock signal, etc., at the same time, these circuits will be simulated in spectre and hspice. at last, the whole cascaded modulator will do behavioral level simulation by matlab soft and simulink toolbox

    本論文中，首先介紹模數轉換器的各種參數的意義，以及一階sigma - delta調制器和高階sigma - delta調制器的原理;給出解決高階單環sigma - delta調制器不穩定性的方案，引入級聯結構調制器，特別針對級聯結構調制器中的失配和開關電容積分器的非理想特性進行詳細的討論;本設計的sigma - delta調制器採用2 - 1級聯結構和一位量化器，調制器採用全差分開關電容電路實現;同時對整個調制器的各個模塊進行了電路設計，包括跨導放大器、開關電容積分器、量化器、兩相非交疊時鐘等，並利用hspice和spectre模擬工具對這些電路進行模擬測試;最後，利用matlab軟體和simulink工具對整個級聯調制器進行行為級模擬。
  3. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  4. Thirdly, the paper discusses the driver of the peripheral equipment, how to port the uc / os - n and uclinux, h. 323 protocol and the application of the system in the digital speech classroom. also some software and hardware measure are adopted to enhance the system stability. at last, the shortcoming and the something to be improved are given. dsp can be used to realize real - time speech coding algorithm, and after porting ( ac / os - n, arm can manage the keyboard, the lcd and the ethernet peripheral etc. then the embedded network system with specific purpose can be used in others fields, such as pda, set of top, web tv, ect

    在實際設計實現中，為提高系統軟、硬體整體穩定性和可靠性，使用了以下幾種方法： （ 1 ）低電壓復位、抗電源抖動能力、增加時鐘監測電路、抗電磁干擾能力、散熱等技術； （ 2 ）多層pcb設計，線路板結構緊湊，電源部分採用數字5v 、 3 . 3v 、 3v 、 1 . 8v和模擬5v多電源供電； （ 3 ）選用表面貼和bga封裝的器件； （ 4 ）按照軟體工程的要求進行系統分析，規劃系統框圖、流程分析、模塊劃分，減小了不同模塊的相關性，從而最大限度避免了錯誤的發生。
  5. The analog signals are regulated to satisfy the system and analog - to - digital converter ( adc ) ; dsp is the core part and is connected with adcs, a controller of ethernet, a rs - 485 bus transceiver, a can bus transceiver and a clock. the real - time data is disposed by dsp and is transferred to the upper computer when the alarm is happened

    模擬信號調理模塊對輸入的信號進行調理，以達到系統和模數轉換器（ adc ）采樣的要求; dsp作為系統的核心部件，外擴了adc 、以太網控制器、 rs - 485總線收發器、 can總線收發器和時鐘晶元， dsp對實時數據進行處理，當報警發生時將實時數據通過以太網上傳給上位機。
  6. Make the minimum of p or simulated figures show a big bell, but still audible timekeeping, as london s " stupid bell, " the same. main functions are : - open lid can

    同時能使小p顯示一個大的數字或模擬鐘，而且還能發聲報時，就像倫敦的「大笨鐘」一樣。
  7. In the last part of this paper, simulation is given to show the performances of the clock recovery methods. the results prove the good jitter performances of the methods

    從模擬結果可以看出，同步時鐘統計恢復法具有很好的抖動性能，可以作為gpon系統tdm接入的一種高效時鐘恢復方案。
  8. Clock recovery is an important and difficult part of tdm access, so the thesis will emphasize on it. and two methods of clock recovery are proposed in the thesis

    然後，本文對同步時鐘統計恢復法進行了分析，推導出了時鐘信號低頻抖動的時域和頻域特性公式，並利用matlab對低頻特性進行了模擬分析。
  9. In this paper, the design of a specific chip for circuit emulation based on ip is put forward and realized and the main functional modules and the key algorithms including an all - digital adaptive clock recovery method and a dynamic depth buffer algorithm are described in detail

    文章根據相關標準提出並實現了一種電路模擬專用晶元的設計方案，並對其中主要功能模塊和關鍵演算法作出了詳細說明，包括一種全數字的自適應時鐘恢復方法、動態深度緩沖演算法等。
  10. Adopts vdsm process technology however two outstanding problems are faced to ic layout design when the feature size reaches to 0. 18 m or lower : 1. timing convergence problem seriously affects the circuits schedule, and the interconnect - delay has exceeded more than 70 % of the total circuits ’ delay. 2. si problem, usually it consists two aspects of ir - drop and crosstalk. these problems often affect the chip function after tapout

    本篇論文就是針對超深亞微米階段soc晶元後端設計所面臨的挑戰，提出了運用連續收斂的布局布線策略，尤其是虛擬原型的設計理論，來快速驗證布局，進而提高布線的成功率，並且提出了一種改進的布局評估模型，提高對soc晶元預測布線的準確度;同時，對于時鐘驅動元件選擇，文中提出了一種基於正態分佈模型來達到更有效的選取。
  11. Combined with the orcad pspice software, it also simulates the clock pulse circuits and relay circuits on the motherboard. the simulation results can satisfy the requirement of the circuit design

    並對母板上的時鐘脈沖電路、繼電器電路應用orcadpspice進行了模擬模擬，模擬結果符合電路設計要求。
  12. Of course the sampling clock is itself a digital signal

    時鐘本身也是數字信號，也會干擾模擬電路。
  13. Based on the analysis of the data and information from the field observations and lab experiments, the results were as follows : ( 1 ) the results of the simulated rainfall and runoff erosion experiments in lab. under the design experiment conditions including the constant rainfall intensities of 1. 0, 2. 0, 3. 0mm / min and the rainfall durations of 30, 70 minutes and with soil moisture content 9. 5 % or 10. 0 % for dry situation, as well as with the soil moisture content 19. 0 % or 20. 0 % for wet situation, the soil erosion increased nonlinearly with the rainfall intensity, and the rainfall duration. the results of the experiments indicated that the amount of soil erosion caused by the simulated rainfall and runoff on the dry - soil slope was more than that on the wet - soil slope

    通過實地觀測及室內試驗資料分析，得到如下研究成果： 1 、室內模擬降雨徑流對戧坡的侵蝕試驗研究結果在定雨強為1 . 0 、 2 . 0 、 3 . 0mm min ，降雨歷時30 、 70分鐘，干土含水量為9 . 5 10 . 0 ，濕土含水量為19 . 0 20 . 0的條件下，侵蝕量與雨強成非線性正比關系；雨強大，侵蝕量大；降雨歷時長，侵蝕量也大；堤坡含水量大時，侵蝕量小，堤坡含水量小時侵蝕量大。
  14. It had also used vhdl language to carry through the timing simulation about hvct and digital clock. the simulation had the same result to the theory. it had established stability foundation to the future chip simulation

    並以實際應用為例，用其對高壓電流互感器和數字鐘進行了時序模擬，模擬結果與理論一致，為進一步的晶元模擬奠定了堅實的基礎。
  15. According to the request of this subject, we have developed the system hardware and software for the slave device and the inspection software running on the pc. in this paper all of the followings is illustrated detailedly, such as the research on the principles of measurement and its realization, three means of water - level measurement that are separately based on photo electricity coder, pressure sensor and potentiometer ; selection of the microchip, we choose an advanced integrated soc ( system on chip ) microchip c8051f021 as the main controller ; realization of signal sampling, processing and its conversion in the mcu ; application of high precision 16 bits adc cmos chip - - ad7705 in our system, designing its interface with the microchip and relevant program ; using a trickle charge timekeeping chip ds1302 in the system which can provide time norm and designing of its i / o interface and program ; additionally, a 4 ~ 20ma current output channel to provide system check - up using ad421. in the system, ad421, ad7705 and the microchip compose spi bus ; to communicate with the master pc, here we use two ways which are separately rs232 and rs485 ; moreover, there are alarm unit, keyboard unit, power supply inspection unit and voltage norm providing unit in the system

    針對研製任務的要求，課題期間研製了下位機系統硬體和軟體，開發了上位機監控軟體，其中所作的具體工作包括：測量原理的研究和在系統中的實現，在本次設計中用三種方法來進行水位測量，分別是旋轉編碼器法、液位壓力傳感器法和可變電阻器法；主控晶元的選擇，我們選用了高集成度的混合信號系統級晶元c8051f021 ；實現了信號的採集和處理，包括信號的轉換和在單片機內的運算；高集成度16位模數轉換晶元ad7705在系統中的應用，我們完成了它與單片機的介面設計及程序編制任務；精確時鐘晶元ds1302在系統中的應用，在此，我們實現了用單片機的i o口與ds1302的連接和在軟體中對時序的模擬，該晶元的應用給整臺儀器提供了時間基準，方便了儀器的使用；另外，針對研製任務的要求，還給系統加上了一路4 20ma模擬信號電流環的輸出電路來提供系統監測，該部分的實現是通過採用ad421晶元來完成的，本設計中完成了ad421與單片機的spi介面任務，協調了它與ad7705晶元和單片機共同構成的spi總線系統的關系，並完成了程序設計；與上位機的通信介面設計，該部分通過兩種方法實現： rs232通信方式和rs485通信方式；系統設計方面還包括報警電路設計、操作鍵盤設計、電源監控電路設計、電壓基準電路的設計。
  16. 3. with time series simulation software, the cpu ’ s i / o ports simulate i2c bus and exchange data with clock chips, temperature humidity sensors, memory chips and other devices

    3 、採用軟體模擬時序使cpu的i / o口模擬i2c總線，實現了單片機與時鐘晶元、溫濕度傳感器、存儲晶元等器件的數據交換。
  17. According to different function, the hardware part is divided into processor module, analog signals input and converting module, digital signals module, communication module, clock module and display module

    按照功能的不同，硬體劃分成處理器系統模塊、模擬信號輸入和轉換模塊、開關量輸入輸出模塊、通信模塊、時鐘模塊、鍵盤顯示模塊、電源模塊。
  18. Compared with manual method, it takes only five minutes to establish a schedule by means of the model. meanwhile, optimization of schedule can be a scheme that can save the time of process from smelting to continuous casting

    利用煉鋼連鑄生產調度模擬時間petri網模型制定調度計劃所需的時間為5分鐘；優化調度計劃可以提供一種縮短煉鋼連鑄工藝流程作業時間的方案。
  19. At the logic synthesis stage, we make some research on the principles of logic synthesis at first, then by utilizing tsmc0. 25um process, choosing the worst case that the workable temperature can be high to 125 degrees centigrade and the supply voltage is as low as 2. 25v, and introducing the wireload library for effectively simulating delay and power consumption of wire connection, and taking the same clocks as in simulation, the critical path is 15. 3ns and the chip area is 0. 395mm2

    在進行邏輯綜合時首先對邏輯綜合的原理作了一定的了解，然後利用tsmc的0 . 25 m的工藝庫，工作電壓為2 . 25v ，工作溫度最高可達到125攝氏度的最壞情況下，進行邏輯綜合時引入了wireload庫以便有效的模擬連線所引起的延遲及功耗，採用與模擬時相同的時鐘，關鍵路徑為15 . 3ns ，晶元面積為0 . 395mm ~ 2 。
  20. An example of a custom control is a clock control that duplicates the appearance and behavior of an analog clock

    時鐘控制項即是一個自定義控制項，它復制模擬時鐘的外觀和行為。
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