模擬編譯系統 的英文怎麼說

中文拼音 [mónǐbiānyìxìtǒng]
模擬編譯系統 英文
analog compiler system
  • 模 : 模名詞1. （模子） mould; pattern; matrix 2. （姓氏） a surname
  • 擬 : 動詞1. （設計; 起草） draw up; draft 2. （打算; 想要） intend; plan 3. （模仿） imitate
  • 編 : Ⅰ動詞1 （編織） weave; plait; braid 2 （組織; 排列） make a list; arrange in a list; organize; gr...
  • 譯 : 動詞（翻譯） translate; interpret
  • 系 : 系動詞（打結; 扣） tie; fasten; do up; button up
  • 統 : Ⅰ名詞1 （事物間連續的關系） interconnected system 2 （衣服等的筒狀部分） any tube shaped part of ...
  • 模擬 : imitate; simulate; analog; analogy; imitation; simulation模擬艙 boilerplate; 模擬電路 [電學] circ...
  • 編譯 : [計算機] compile; translate and edit編譯程序 compiler; compile programme; compiling routine; 編譯...
  • 系統 : 1. （按一定關系組成的同類事物） system 2. （有條理的;有系統的） systematic
  1. We design a complier of parametric and random context sensitive l - system to simulate the development of plants and interpret the rules that decide the way plants grow. we also extend the l - system with the environment factor

    我們為模擬植物生長而編寫了l系統編譯器來實現可定義規則的植物造型，並把隨機因子和環境參數擴充到l系統中。
  2. The thesis mainly focuses on the encoding and decoding to the systemic convolutional code with programming language, which is prescribed in the intelsat iess 309 standard

    本文主要針對intelsatiess309協議標準中所採用的系統卷積碼，模擬並編程實現其編碼和譯碼。
  3. The iess 309 standard indicates two decoding methods, we focus on the systemic convolutional code with long encoding restriction which is 36 bit and adopt the fano sequential decoding algorithm to implement the decoder

    在協議中規定了兩種譯碼的方式，我們主要是針對編碼約束度為36的系統卷積碼，採用fano序列譯碼演算法來實現其譯碼，並進行了模擬。
  4. Part two : design the schematic of the intelligent communication card ; to apply protel99 software to design sch and pcb charts, then send them to the factory ; to debug on the hardware and test on can bus chip ; to program assemble language control and can bus communication software of the intelligent communication card and debug on the super ice16 simulator ; to utilize the super ice 16 simulator to debug the control programs of the communication card online ; link to control card and debug the can bus communication program online ; to debug the system on eprom

    第二部分：設計can總線智能通信卡的硬體電路，應用protel99設計軟體繪制原理圖及印刷電路板圖，並送廠製作板卡電路板:智能通信卡硬體製作和can總線晶元調試;編寫通信卡控制及can總線通信匯編語言程序並編譯;在superice16模擬器上在線模擬調試控製程序;連接系統控制卡，模擬調試can總線通信程序;程序燒入eprom晶元，進行系統eprom模擬調試;介面系統驅動程序及測試軟體調試。
  5. Analog compiler system

    模擬編譯程序系統
  6. Based on pc, this paper develops compiled system and simulative running system of soft plc

    本文以pc為硬體開發平臺，通過編程開發出了軟plc的編譯系統和模擬運行系統。
  7. Finally yet importantly, sctcm is researched which combines sccc with high bandwidth efficiency modular method tcm. besides, the corresponding schemes of encoding and modulating of sctcm, the corresponding demodulating and decoding algorithm, and the performance simulation are also presented

    最後討論了sccc與高頻帶利用率調制方式結合的sctcm ，研究了適用於sctcm系統的編碼調制方案和解調譯碼演算法，並給出了性能模擬。
  8. It is in dire solved need of opening up nc machining simulating system in manufacturing that there are maturity function and better real time. aiming at the simulating system study of 5 - axis numerical control milling of sajo12000p, the paper introduces the function modules of simulation system of nc machining., including interface module data processing data chain module timely controlling and roming module, and by this way we accomplished the basic function of numerical control machining

    因此開發功能完備、實用性強的數控加工過程模擬模擬系統成為當前製造業急需解決的一個問題本文以數控技術實驗室的saj012000p五坐標加工中心為模擬對象，針對其開發一套數控模擬軟體，本人承擔了整個模擬系統的cnc控制軟體的開發工作，針對cnc系統軟體的人機交互界面的建立、 nc代碼的編譯、編譯指令的數據處理、插補、進程問數據鏈的傳輸加載、機床模擬運動按照nc指令的適時控制等功能子模塊進行了開發研究。
  9. We put the emphases on the soft output viterbi algorithm ( sova ), which is one of turbo code ’ s decoding algorithms, and presents the derivation and computation step of the sova decoding algorithm. after presenting sova and map decoding algorithms and analyzing four kinds of decoding algorithms, the paper makes a comparison among the different decoding algorithms by emulation analysis, and analyzes the time complexity of various algorithms, and then contrasts them. in the last part of this paper, according to the criterion recommended by the consultative committee for space data systems ( ccsds ), including code rate,

    根據空間數據系統顧問委員會（ ccsds ）為turbo碼應用於深空通信系統推薦的標準，包括碼率、碼塊大小、分量碼類型、約束長度、碼生成多項式，以及交織器的選擇等參數的建議以及sova譯碼演算法的理論基礎，設計了sova演算法的實現結構，通過模擬驗證了本文所採用的turbo碼的性能，從而證明turbo碼確實是一種很好的通道糾錯編碼方式，它適用於要求功耗低或信噪比低的深空通信系統中。
  10. The main two process of the development on system is as follows : part one : using prote199 software to design the sch chart of the analog signal input card and complete pcb charts, then have them made in factory ; to debug on the hardware ; to program assemble language control software of the analog signal input card and debug on the super ice 16 simulator ; to utilize the super ice 16 simulator to link card to debug the control programs online ; to embed the control program debugged successfully into eprom and debug the system on eprom

    系統研製開發過程主要分兩大部分：第一部分：應用protel99設計軟體設計模擬量輸入卡的硬體原理，規劃設計印刷電路板圖並送廠製作板卡電路板；模擬量輸入卡硬體製作和調試；編寫模擬量輸入卡匯編語言控製程序，在superice16模擬器上編譯調試；編譯后的控製程序在superice16模擬器上以在線方式模擬調試；模擬調試成功的控製程序燒入eprom晶元，進行系統eprom模擬調試。
  11. The most advance software - engineering methodology was presented, for example the oop, com, compiler technology and so on., which are used to design and develop the component modeling and simulation application framework of the tgcs

    本論文模擬軟體的實現採用了最先進的軟體工程方法? ?面向對象技術、組件技術、編譯技術，由此設計和開發了的魚雷制導系統模擬環境。
  12. Before the development of the system, the article describes the above - mentioned aspects, as the bases of the system development. the article emphasizes related auto - controlling technologies : open - 100p and close - 100p, and control mode of negative - feedback, the scatter and quantization of the simulate signal, the conception of a / d and d / a conversion and code / encode, the basic sampling principles of the simulate signal. the article introduces the operation method and process of the system by means of the load spectrum

    文章對相關的理論進行了陳述，以作為系統開發的理論依據，重點闡述了自動控制系統中包括開環閉環在內的幾大主要控制模式，以及有關的負反饋控制方式，模擬信號的離散與量化，模數轉換、數模轉換、編碼譯碼的概念，及模擬信號采樣的基本原理? ?采樣定理，並以載荷譜法為例，簡述了所研究的系統將要採取的工作方式及工作過程。
  13. In detail, they are bit - interleaved coded modulation ( with iterative decoding ), low - density parity - check codes and stf technology. by the performance analysis of bicm ( - id ), which can make code and modulation optimal separately, and achieve maximum possible coding diversity as well as modulation gain, guidelines for its design and an easy algorithm for siso are proposed. design of capacity - approaching of ldpc codes and efficient encoding of them as well as several kinds of its decoding algorithms are investigated

    具體的講，就是討論了基於比特交織的編碼調制技術，並給出了映射方式的設計準則以及核心模塊siso的一種簡單的f - map演算法；研究了編碼最小漢明距隨碼長線性增加的ldpc碼的幾個方面的問題，包括接近香農限碼子集的度分佈對的設計、有效編碼器的實現和各種譯碼演算法的優缺點，並對基於ldpc碼的bicm應用於ofdm傳輸系統中的性能進行了模擬。
  14. Study of the compiler and emulation for planer - type wedm based on 3d platform

    平臺龍門式電火花線切割編譯模擬系統的研究
  15. Considering the after cooperation development, the project adopts the system frame based on the components programming technique. the project is divided into three self - existent modules, which made in the mode of component : the module of control task understanding, the module of control system generation and the module of control simulation. they are developed, compiled, debugged and tested separately

    為了后續的協作開發，系統採用了基於組件編程技術的系統架構，將開發工程劃分為控制任務理解模塊、控制系統生成模塊、控制模擬模塊3個各自獨立的組件單獨開發、編譯、調試和測試，當所有的組件開發完成後，把它們組合在一起就可以得到完整的應用系統。
  16. This system is realized by cpld which can get rid of the disadvantages in one - time design including property liable to jamming, long sampling period, and poor working stability. its sampling period is up to 500ns at least and output delay is only 19. 5ns. a stable period of pulse coming out of quadruple - frequency differential circle belongs to it

    完成了用vhdl硬體描述語言對全數字轉速位置測量子系統的設計，並用max ? plusii軟體進行了編譯和波形模擬，在cpld （ max7000 ）得到實現，該系統克服以往設計中存在的易受干擾、工作穩定性差、采樣周期太長等的缺點，輸出延時僅為19 . 5ns ，采樣最低周期可達到500ns ，且四倍頻微分電路獲得的脈沖周期穩定。
  17. This paper achieves expected digital filters program through algorithms descriptions, analyzing and realization, simulation, comparing on error and speed. this paper achieves expected digital interpolations program through algorithms descriptions, analyzing and realization, simulation, comparing on error and speed

    本文應用matlab信號處理工具箱，通過對數字濾波器演算法的描述、演算法分析、實驗模擬、誤差比較，及性能比較，最終獲得滿足要求的數字濾波程序，並編譯成c + +源代碼文件配合主程序調用，完成了系統聯調。
  18. Space - time block codes ( stbc ) based on orthogonal design has attracts enough attentions in its applications in mimo - ofdm systems for its full diversity exploiting and low coding / decoding complexity. these applications include not only system performance improvement, but also reduction of the peak to average power ratio in mimo - ofdm systems. under these backgrounds, this paper first studies space - time block codes under the single carrier, flat fading situation, discusses the encoding / decoding principle and its performance under different channels. then, the author focused on the performance of space - time codes under time selective and frequency selective channels, uncovered the fundamental cause of how maximum doppler shift and power delay profile influences the performance of space - time codes through deduction and simulation

    在上述背景下，本文以單載波，平坦衰落通道下的空時分組碼為切入點，深入分析了其編譯碼原理和在不同通道情況下的性能;以此為基礎，後文展開了對空時分組碼在多載波，時間選擇性和頻率選擇性衰落通道下的性能研究，通過理論推導和充分的模擬，揭示了空時/頻分組碼在時頻選擇性衰落通道中的性能變化的根本原因;在以上對多載波系統中空時分組碼的研究的過程中，作者發現了空時分組碼在降低系統峰平比方面應用的可行性，提出了一種降低峰平比的新方法。
  19. After a great amount of detailed computer simulations and concise qualitative and quantitative theoretical analysis, the turbo codes " parameters and fpga specific hardware implementation architecture suitable for being integrated into dtv systems are determined. furthermore, the codec is completely designed with verilog hdl, ending with an occupation of less than a 600 - thousand - gate fpga chip. at this lowest hardware cost, a white noise snr threshold of 1. 8db at a net stream rate of 6mbps is achieved, which exceeds all other existent dtv systems " performance

    經過大量詳細的計算機軟體模擬和簡明扼要的定性與定量的理論分析，最終確定了數字電視系統中適合採用的turbo碼參數及針對fpga特殊構架的硬體實現結構，並用verilog硬體描述語言完成了turbo碼編譯碼器的完整設計，以佔用不到一片60萬門fpga晶元的較少的硬體資源取得了在6mbps凈碼率下1 . 8db的白噪聲信噪比門限這一遠遠超過現有任何數字電視系統的性能。
  20. Based on the traditional complier testing, this paper proposes a method that introduces a reference compiler into compiler testing. by collecting dynamic data information ( ddi ) files in software simulator, bugs in tested compiler can be located in function level

    本文最後對編譯系統的驗證進行了研究，提出引入參考編譯器和參考模擬器的測試方法，並通過在模擬器中插裝代碼生成動態數據信息（ ddi ）文件，能夠將錯誤定位到函數級，給編譯器的調試帶來很大的便利。
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