溝道電阻 的英文怎麼說
中文拼音 [gōudàodiànzǔ]
溝道電阻
英文
channel resistance- 溝 : 名詞1 （挖掘的水道或工事） channel; ditch; gutter; trench 2 （淺槽;似溝的窪處） groove; rut; furr...
- 道 : Ⅰ名詞（道路） road; way; route; path 2 （水流通過的途徑） channel; course 3 （方向; 方法; 道理） ...
- 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
- 阻 : 動詞（阻擋; 阻礙） block; hinder; impede; obstruct
- 電阻 : （物質阻礙電流通過的性質） resistance; electric resistance （電路中兩點間在一定壓力下決定電流強度...
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In the model of on - resistance, we have considered the lateral doping distribution in ldmos channel and vertical doping distribution in drift region. then we provide the explicit dependence between on - resistance and doping distribution parameter
導通電阻模型考慮了ldmos的溝道橫向雜質分佈和漂移區雜質縱向分佈的結構特點，給出了導通電阻與雜質分佈參數的明確函數關系。The source drain extension ( sde ) structure and its reliability are thoroughly studied. first, it is shown that the sde structure can suppress short channel effect effectively and the parasitic resistance at the sde region has an effect on performance. it is proposed that increasing the dose condition in the sde region can reduce the parasitic resistance and should be adopted to achieve high performance for deep submicron devices
本文對深亞微米源漏擴展mos器件結構及其可靠性進行了深入研究，首先通過模擬驗證了源漏擴展（ sde ）結構對短溝道效應的抑制， sde區寄生電阻對器件性能的影響以及sde區摻雜濃度的提高對器件性能的改善，指出了器件尺寸進一步減小后，提高源漏擴展區摻雜濃度的必要性。Compared with the similar research results, the weighted control ic here has the following characteristics : ( 1 ) the circuit structure is simpler ; ( 2 ) the chip ' s fabrication is compatible with standard cmos process ; ( 3 ) n - mosfets with high w / l ratio and short channels are used for weighting and output to reduce the insertion loss ; ( 4 ) the weighting factor varies in a relatively wide range with the controlling signals ; ( 5 ) input and output impedance approach 50 in low frequency ( e. g. 50mhz ), while in higher frequency they slightly deviate from 50, hence the energy reflection lower than 0. 1 ; ( 6 ) it completes the functions of sampling, weighting, controlling and summing of high frequency analog signals
它的加權控制電路與已報道的相關電路相比具有如下特點：電路結構簡單；製造工藝與普通cmos工藝兼容：短溝道，高寬長比的nmos晶體管具有低的通導電阻，將其作為加權、輸出器件可降低由電路引起的插入損耗；改變加權信號，可實現權值在較大范圍內的連續變化；輸入、輸出阻抗在低頻（如50mhz ）下接近50 ，而在高頻下略有偏離50 ，但反射系數均低於0 . 1 ；實現了對高頻信號的取樣、加權、控制、疊加功能的迭加。
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