漏極 的英文怎麼說

中文拼音 [lóují]
漏極 英文
drain channel junction
  • 漏 : Ⅰ動詞1 （從孔或縫中滴下、透出或掉出） leak; drip 2 （泄漏） divulge; disclose; leak 3 （遺漏） le...
  • 極 : i 名詞1 （頂點; 盡頭） the utmost point; extreme 2 （地球的南北兩端; 磁體的兩端; 電源或電器上電流...
  1. Based on the hydrodynamic energy transport model, the influence of variation of negative junction depth caused by concave depth on the characteristics of deep - sub - micron pmosfet has been studied. the results are explained by the interior physical mechanism and compared with that caused by the source / drain depth. research results indicate that with the increase of negative junction depth ( due to the increase of groove depth ), the threshold voltage increases, the sub - threshold characteristics and the drain current driving capability degrade, and the hot carrier immunity becomes better in deep - sub - micron pmosfet. the short - channel - effect suppression and hot - carrier - effect immunity are better, while the degradation of drain current driving ability is smaller than those with the increase of depth of negative junction caused by source / drain junction shallow. so the variation of concave depth is of great advantage to improve the characteristics of grooved - gate mosfet

    基於能量輸運模型對由凹槽深度改變引起的負結深的變化對深亞微米槽柵pmosfet性能的影響進行了分析，對所得結果從器件內部物理機制上進行了討論，最後與由漏源結深變化導致的負結深的改變對器件特性的影響進行了對比.研究結果表明隨著負結深（凹槽深度）的增大，槽柵器件的閾值電壓升高，亞閾斜率退化，漏極驅動能力減弱，器件短溝道效應的抑制更為有效，抗熱載流子性能的提高較大，且器件的漏極驅動能力的退化要比改變結深小.因此，改變槽深加大負結深更有利於器件性能的提高
  2. In gan hemt drain pulse current collapse experiments, drain current under pulse condition collapsed about 50 % than direct current condition and the pulse signal frequency affected little on current collapse. when gate voltage is small, the relationship between pulse width and drain current is i0 ( + t / 16 )

    在ganhemt漏極脈沖電流崩塌測試中，發現脈沖條件下漏極電流比直流時減小大約50 % ;脈沖信號頻率對電流崩塌效應影響較小;當柵壓較小時，隨著脈沖寬度的改變漏極電流按i0 （ + t / 16 ）的規律變化。
  3. The main work of this thesis analyzes the organic static induction transistor ' s operational mechanism, and researchs the change of gate length, change of gate - drain distance and change of electric channel breadth for operational characteristics influence of organic static induction transistor

    本論文的主要工作是解析有機靜電感應三極體的工作機理，並研究了柵極長度變化、柵漏極間距變化和導電溝道的寬度變化對有機靜電感應三極體工作特性的影響。
  4. It is believed that p - si tft will be the main type in the future panel display. among the process of manufacture p - si tft, the source and drain will have the superposition with grid for the reason of machine ’ s alignment error. the superposition will bring superposition capacitance and it will badly cut down the electric performance

    在制備多晶硅tft時，由於機器的套準誤差會在柵極與源、漏極之間產生重疊部分，這樣就造成了柵源、柵漏之間的交疊電容，交疊電容的存在嚴重影響了多晶硅tft的性能，而利用自對準工藝制備的多晶硅tft則避免了交疊電容的產生。
  5. In gan hemt gate pulse experiments, drain current under pulse conditon collapsed about 47 % than direct current condition and the pulse width affected little on current collapse. the relationship between drain current and pulse frequency is ncoxw [ m + ( n + k ? ) vgs + ( n + k ? ) vgs2 ] ( vgs - vth ) 2 / l

    在ganhemt柵極脈沖電流崩塌測試中，觀察到柵脈沖條件下漏極電流比直流情況下減小了47 % ;隨著信號頻率的改變，漏極電流按ncoxw [ m + （ n + k
  6. Based on the hydrodynamics energy transport model, the degradation induced by donor interface state is analyzed for deep - sub - micron grooved - gate and conventional planar pmosfet with different channel doping density. the simulation results indicate that the degradation induced by the same interface state density in grooved - gate pmosfet is larger than that in planar pmosfet, and for both devices of different structure, the impact of n type accepted interface state on device performance is far larger than that of p type. it also manifests that the degradation is different for the device with different channel doping density. the shift of drain current induced by same interface states density increases with the increase of channel do - ping density

    基於流體動力學能量輸運模型，對溝道雜質濃度不同的深亞微米槽柵和平面pmosfet中施主型界面態引起的器件特性的退化進行了研究.研究結果表明同樣濃度的界面態密度在槽柵器件中引起的器件特性的漂移遠大於平面器件，且電子施主界面態密度對器件特性的影響遠大於空穴界面態.特別是溝道雜質濃度不同，界面態引起的器件特性的退化不同.溝道摻雜濃度提高，同樣的界面態密度造成的漏極特性漂移增大
  7. Under hot carrier stress, device degradation is the consequence of hot carrier induced defect generation locally at drain side

    在熱載流子應力條件下，器件的退化主要是由於在漏極附近由熱載流子產生的損傷缺陷引起的。
  8. Small signal jfets work very well as low - leakage diodes by connecting drain & source together in log current - to - voltage converters and low leakage input protection

    在對數電流-電壓轉換器和低漏電流輸入保護電路中，通過連接小信號jfets的漏極和源極，可以使之作為低漏電流二極體很好的使用。
  9. In fet devices, the presence of an electrical field at the gate moderates the flow between the source and drain

    在fet器件中，柵極電場的存在會調節源極和漏極之間的電流。
  10. Ti ? the resistance measured across the channel drain and source ( or input and output ) of a bus - switch device

    測量總線開關器件指定通道的源漏極間（或輸入和輸出）所得到的阻抗。
  11. Quasi - static capacitance has been measured, when drain voltage is 0v, and gate voltage changes from ? 5v to 0v, the surface peak

    採用應力測試方法，獲得了algan / ganhemt漏極電流隨時間的變化。
  12. In the fifth chapter the shunt negative feedback is presented, and a low noise amplifier whose operating frequency is 0. 2ghz 2ghz is developed

    第五章分析了漏極並聯負反饋在寬帶低噪聲放大器設計中的作用和原理，並設計、製作了0 . 2ghz 2ghz低噪聲放大器。
  13. Under high drain voltage condition, the results proved that channel electrons are easily ejected into gan buffer layer and be trapped to induce current collapse

    在大漏極電壓條件下，溝道電子易於注入到gan緩沖層中，並被緩沖層中的陷阱所俘獲，耗盡二維電子氣，從而導致電流崩塌效應。
  14. For low distortion, the drains ( or collectors ) of a differential amp " s front - end should be bootstrapped to the source ( or emitter ) so that the voltages on the part are not modulated by the input signal

    為了得到低失真，差分放大器前端的漏極（或集電極）應該被引導到源極（或射極） ，這樣埠電壓就不會被輸入信號調制了。
  15. Under a unified model of carrier transport over trap state established potential barrier at drain side, device degradation behavior such as asymmetric on - current recovery and threshold voltage degradation can be understood

    我們通過載流子在漏極附加陷阱態勢壘的輸運模型，解釋了器件在應力后出現的閾值電壓的退化現象和非對稱性開態電流恢復現象。
  16. The result of the test for dynamic breakdown characteristics reveal that breakdown voltage increases as the lengths of the pulses applied to the gate and drain electrodes increase. this could be mainly due to the influence of surface states

    Gaasmesfet動態擊穿特性測試結果表明， gaasmesfet的擊穿電壓隨柵極與漏極上所加脈沖電壓寬度的增大而增大，這主要是因為表面態的原因。
  17. Finally, according to the mosfet ' s parameter degradation due to hot - carrier effects and different application environment of mos devices on analog and digital circuits, the circuit structures for hot - carrier immunity are proposed for digital applications by adding a schottky diode in series with the drain of the nmosfet suffered heavily from hot - carrier degradation.,

    即在受熱載流子退化效應較嚴重的n mosfet漏極串聯一肖特基二極體的新型cmos數字電路結構和串聯一工作于線性區的常開n mosfet的mos模擬電路結構。經spice及電路可靠性模擬軟體bert2
  18. The oil spill off the coast of alaska has greatly upset the ecosystem there

    在阿拉斯加近海的原油泄漏極大地破壞了那裡的生態系統。
  19. Usually series mode is used in low frequency circuit while bypass mode is used in high frequency circuit, series mode micro - switch with cantilever structure is similar to an fet, when voltage is applied on gate, and the fet will be turned on between source and drain

    有靜電電壓作用在梁和底面電極時，梁發生偏轉，在源極和漏極之間實現導通，常用於自控和通信系統的信號通路空氣橋旁路開關主要用於微波段信號的通路。
  20. Finally the method of preparation of p - si tft and some useful dates were given. the dissertation includes seven chapters. the first chapter introduces the development of tft ; the second chapter introduces the principle of tft and its structure ; the third chapter provides the reason of superposition capacitance between s, d and gate ; the fourth chapter introduce the deposition and test method of sinx ; the fifth chapter introduces the fabrication of p - si ; the sixth chapter studies the fabrication techniques of p - si tft and some parameters ; the seventh chapter is a conclusion of the research

    本文一共分為七章:第一章介紹了本論文的研究背景、研究意義、主要工作以及國內外的研究進展;第二章介紹了tft的結構和工作原理;第三章介紹了柵極與源、漏極之間疊加電容產生的原因和自對準工藝;第四章介紹了氮化硅的制備方法和測試方法;第五章介紹了多晶硅tft有源層的制備方法並對各種晶化機理做了介紹;第六章主要對利用自對準工藝制備tft的工藝進行研究，並對制備出來的樣品進行了測試;第七章對全文進行總結。
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