硬存器 的英文怎麼說
中文拼音 [yìngcúnqì]
硬存器
英文
hardware register-
1. may copy photos and data from cards to built - in harddisk without pc
1 .毋須電腦，可直接將記憶卡復制數碼相片到此儲存器內的硬碟Co - work with hardware engineer and customer to provide well - defined api to encapsulate the hardware registers operation to a hardware abstraction layer
通過和硬體工程師及客戶緊密合作，提供定義良好的api來封裝寄存器操作，實現對硬體平臺的抽象。The core is based on harvard architecture with 16 - bit instruction length and 8 - bit data length. the performance of mcu has been improved greatly by introducing single - clock - cycle instructions, setting multiple high - speed working registers and replacing micro - program with direct logic block etc. to keep the mcu core reusable and transplantable, the whole mcu core has been coded for synthesis in verilog hdl
該mcu核採用哈佛結構、 16位指令字長和8位數據字長，通過設計單周期指令、在內部設置多個快速寄存器及採用硬布線邏輯代替微程序控制的方法，加快了微處理器的速度，提高了指令的執行效率。On the base of analyzing the sparc instruction set, this paper researches the pipeline technology and the resolution of correlation problems, and these problems were resolved by using the harvard architecture, internal forwarding and delay branch technology
本文在分析sparc指令系統的基礎上，研究了流水技術及其相關問題的解決方法，並通過在硬體上使用哈佛結構、提前寫寄存器的操作時間以及內部前推和延遲轉移等技術較好的解決了結構相關、數據相關和轉移相關的問題。Provides a secure connection between the hard drive and the cable connector via a locking latch mechanism. ideal for
-透過鎖定鎖存器裝置，為硬碟機和電纜連接器之間提供安全的連接。For the real time performance need of the low speed speech compress algorithm and the asic implement of the transfer process between programs, the design is put forward in the paper, in which state registers control the cross access between operator and memory, register windows are used for the parameters transfer, and the technique of hardware controlling is used to avoid pipeline conflict, so that the main problems of the transfer process in tr600 are solved effectively
摘要針對低速率語音壓縮演算法對處理器系統實時處理復雜運算的性能要求，就程序調用過程的asic實現問題進行了對比與分析，進而提出了用層次狀態寄存器控制存取運算元對存儲體交叉訪問的方法，並結合運用寄存器窗口傳遞參數的功能，以及利用空指令硬布線處理流水線沖突的方法，有效地解決了tr600晶元中調用過程存在的主要問題。It presents the verification strategy used in the whole eda design flow of the chip. the simulation on module level ( inc. post - layout ) uses the software event - driven simulator, the simulation of the associated modules or whole system uses cycle - based simulator and hardware emulator, for the gate - level netlist produced by using top - down design flow, the sta tool can analyze the static timing, and more formal verification is used to ensure the correct function
本章還提出了系統在整個eda設計流程中的設計驗證策略方法：模塊級的模擬（包括布線后的模擬）全部採用事件驅動式的軟體模擬工具來驗證，各大模塊的聯合模擬及整個晶元的功能驗證（寄存器傳輸級與門級）使用基於周期的模擬工具和硬體模擬器；對于採用top - down的設計方法得到的門級網表使用專門的靜態時序分析工具來進行時序分析以及採用形式驗證來保證正確的功能。This includes initializing hardware registers, identifying the root device and the amount of dram and flash available in the system, specifying the number of pages available in the system, the filesystem size, and so on
這包括初始化硬體寄存器、標識根設備和系統中可用的dram和閃存的數量、指定系統中可用頁面的數目、文件系統大小等等。Traditional methods such as emulation can do little about it, it has to introduce some new arts. on the path of modern computer and cpu designing, the registers, level 1 cache, level 2 cache on the chip and level 3 cache on the mainboard, plus ram, hard disk or floppy disk or flash disk, make up of the modern multi - hiberarchy storage architecture
現代計算機和cpu設計中， cpu片內的寄存器、一級高速緩存（ level1cache ）和二級高速緩存（ level2cache ） ，主板上的三級高速緩沖，再加上主存，外存（硬盤、軟盤、電子盤等） ，構成了現代計算機的多級存儲體系結構。And more than 70 % hardware are tested during microcode self - test since the execution of micro program can cover other data paths. boundary scan is designed according to ieee1149. 1, and some other instructions such as degug, runbist are provided to support internal fault testing, online debugging and built - in self - test besides the several necessary insructions. internal scan is implemented by partial scan, through this the boundary of logic component and user - cared system registers can be selected to be scanned
Bist用於測試cpu的微碼rom ，其它ram則利用微碼rom中的微程序進行測試，而微程序的運行則可以順帶覆蓋其它數據通路，從而使高達70 %的硬體得到測試;邊界掃描按ieee1149 . 1標準設計，除必備的幾條邊界掃描指令外，還提供了debug 、 runbist等指令以支持內部故障測試、在線調試及內建自測試;內部掃描採用部分掃描策略，選擇邏輯部件的邊界及用戶關心的系統寄存器進行掃描，從而實現了硬體邏輯劃分，方便了后續的測試碼產生和故障模擬，並為在線調試打下了基礎。A device or equipment making possible interoperation between two systems, for example, a hardware component or a common storage register
能夠使兩個系統之間相互運行的一種設備或裝置。例如一種硬體部件或一種公共的存儲寄存器。The result shows that the soft and hard faults will have different significance to the performance of circuits at a wide range of defect size. the relationship between yield and reliability is concerned for a long time
最後以一個4x4的移位寄存器為例，驗證了該方法的有效性，最後的模擬結果給出了在不同粒徑時，軟、硬故障對電路性能影響程度的比較。This text introduced the work patterns and register structure of 80386 processors in detail at first, latterly expounded especially the hardware interrupt handling of windows 98 with the course to the kernel of windows 98 ; then recommended the framework of realization of highly demanding hardware board interrupt handling by revising idt to intercept interrupt handling at hardware layer, subsequently introduced the application and development of vxd technology to achieve interrupt handling overall all situations under the windows 98 platform ; finally introduced the b / s pattern network application development part of this topic, specifically introduced the jsp technology system, elaborated the communication between network application part and the hardware interrupt handling routine combined with the jni technology, and provided partial important program and corresponding commentary
本文首先詳細介紹了80386處理器的工作模式和寄存器結構，接著對windows98的內核進行了相關分析，重點介紹了windows98的硬體中斷處理過程;隨后介紹了通過修改中斷向量表以實現在硬體層截獲中斷來實現高實時性處理的框架，又介紹了windows98下虛擬設備驅動vxd技術的應用與開發，以及中斷全局處理的實現;最後介紹本課題的b / s模式網路應用開發部分，具體介紹了jsp技術體系，並結合jni技術闡述了網路應用與硬體中斷處理程序的通信，並給出部分關鍵程序及其注釋。Qe1 achieve the whole synchronization by software and hardware. during the course of the initialization of the qe1 system, the chip pm4354 can accomplish the task of synchronization of bit, frame and multiframe after the chip initialization by the software. after pm4354 accomplishes the bit synchronization, qel will read the status registers of the pm4354 to get the status of each el circuit and choose recovered clock of the specified the el circuit as the external timing source of the whole htc - 5200an equipment
Qe1系統在系統初始化時，通過軟體完成對硬體晶元pm4354的初始化工作后，便可利用該晶元完成4路e1的同步（位同步、幀同步和復幀同步） ；在pm4354完成時鐘提取的任務后， qe1通過不斷地訪問pm4354的狀態寄存器，獲得每路e1的狀態信息，在時鐘源的選擇原則下，選擇指定e1線路的恢復時鐘作為整個htc - 5200an節點設備的外部參考時鐘，從而解決了htc 5200an的中繼板卡由e1變為qe時所帶來的網同步時鐘源。A raw ( read after write ) dependency loop model is developed in this paper to analyze the raw hazards of register operands in complex pipeline. based on this model, a " dynamic " data forwarding policy is suggested to reduce the pipeline stalls caused by data raw hazards. theoretical analysis and practical experiments both show that the average cpi increment caused by data raw hazards can be reduced effectively by the dynamic data forwarding strategy
對于單發射結構的處理器，降低cpi值的根本途徑在於通過各種軟硬體技術減少流水線的停頓，本文構造了一個raw相關環路模型用於分析流水線中寄存器操作數的raw競爭現象，並提出了一種「動態」數據旁路優化策略，可以最大程度地減少復雜流水線中因數據的raw競爭而導致的互鎖停頓，理論分析和實測結果充分表明「動態」數據旁路機構可以有效地降低流水線因raw互鎖導致的平均cpi增量。A typical calculator chip from rcl semiconductor inc, c9821, is referenced and developed. the chip of the calculator consists of several function units such as rc oscillator, power management module, microprogrammed control unit ( mcu ), register group, lcd driver and keyboard interface
在硬體方面，在完成計算器的功能模塊劃分的基礎上，對包括rc振蕩器、電源模塊、 lcd顯示驅動模塊、鍵盤介面、寄存器組、微程序控制器在內的各個功能模塊的系統結構和電路原理進行了分析，掌握了它們的設計方法。Due to the development of 1c technology, now a complex system can be integrated in a chip called system on chip ( soc ). the design of soc needs new design methodologys and modeling tools. systemc is an open c + + modeling platform promoted by the open systemc initiative, which consists of a well defined set of c + + classes and a simulation kernel, supporting design abstractions at the register - transfer, behavioral, and system levels. the advantages of systemc include the ability for hardware - software co - design, the ability to exchange ip easily and efficiently, and the ability to reuse test benches across different levels of modeling abstraction
系統級晶元的設計需要新的設計方法和建模工具。 systemc是osci （ opensystemcinitiative ）組織制定和維護的一種開放源碼的c + +建模平臺，它由一個定義良好的c + +類庫及模擬內核組成，支持對系統進行寄存器傳輸級，行為級和系統級的描述。 systemc的優點包括對軟硬體聯合設計的支持，更高效和方便的進行ip交換，以及在不同的抽象模型間復用測試基準的能力。With software and hardware co - design method, this paper proposes an algorithm to calculate register lifetime in programs, and the control of writing results back into rf is implemented through an enable control signal provided by instruction encoding at compile time
基於軟硬體協同設計的思想，在研究局部變量生存期演算法的基礎上，本文提出了通過編譯器指令編碼實現對硬體結構的使能控制，即控制流水輸出結果是否寫回寄存器文件，以減少對寄存器文件的寫次數，從而降低寄存器文件埠的讀寫壓力。Integrated hardware ( such as video chips that share system ram ) and parallel port devices can also be problematic
整合的硬體（像是共享的電視薯條系統隨機存取儲存器）和平行埠裝置也可能是棘手的。A method of inte * * cing with hardware that involves repeatedly reading a status register until the device has reached the awaited state
一種硬體交互方法，不斷讀狀態寄存器，直到設備進入等待狀態。分享友人