硬體乘法模塊 的英文怎麼說

中文拼音 [yìngtǐchéngfǎmókuāi]
硬體乘法模塊 英文
hardware multiply module
  • 硬 : 形容詞1 （堅硬） hard; stiff; tough 2 （剛強; 堅定; 強硬） strong; firm; tough; obstinate 3 （勉...
  • 體 : 體構詞成分。
  • 法 : Ⅰ名詞1 （由國家制定或認可的行為規則的總稱） law 2 （方法; 方式） way; method; mode; means 3 （標...
  • 模 : 模名詞1. （模子） mould; pattern; matrix 2. （姓氏） a surname
  • 塊 : 名詞（古時佩帶的玉器） penannular jade ring （worn as an ornament in ancient china）
  • 硬體 : hardware
  • 模塊 : camac module,camac
  1. We select ni / cr alloy resistor as element together with ceramic embedding hearth ; select small flat - and - disc heat - even hubby ceramic sample holder, select ni / cr & ni / si thermoelectric couple ( type k ) as thermoscope with threads 0. 5 mm in diameter which is installed in the middle of the holders symmetrically ; select aluminum silicate fire - retardant fiber as materials for heat preservation ; design some hardware, for example temperature controller & transporter, signal amplifier etc ; design controlling curve to heat stove ; and introduce the method of least squares nonlinear regression and subsection function to deal with data. in order to obtain the reasonable operation conditions and operation curve, we have also done many theory analysis and experiment discussions

    通過理論和試驗探討，選用鎳鉻合金電阻絲作為加熱元件，配以陶瓷質埋入式爐膛；選用陶瓷質小尺寸扁平?圓盤均熱塊體型樣品支持器；選用0 . 5mm絲徑鎳鉻?鎳硅熱電偶（ k ）作為測溫元件；熱電偶對稱安置在樣品支持器容器的中部；選用硅酸鋁耐火纖維作保溫材料；合理選用和設計了溫度控制器、溫度變送器、信號放大電路等硬體；採用升溫曲線來控制爐膛供熱過程；採用最小二乘法非線性回歸與分段函數相結合的曲線模擬方法，進行圖形處理。
  2. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  3. It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ), 5 - stage pipeline, hardware multiplier and divider, interrupt controller, 16 - bit i / o port and a flexible memory controller. new modules can easily be added using the on - chip amba ahb / apb buses. it has flexible peripheral interfaces, so can be used as an independent processor in the board - level application or as a core in the asic design

    它遵照ieee - 1745 （ sparcv8 ）的結構，針對嵌入式應用具有以下特點：採用分離的指令和數據cache （哈佛結構） ，五級流水，硬體乘法器和除法器，中斷控制器， 16位的i / o埠和靈活的內存控制器，具有較強的異常處理功能，新模塊可以輕松的通過片上的ambaahb / apb總線添加。
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