硬體乘法 的英文怎麼說

中文拼音 [yìngtǐchéngfǎ]
硬體乘法 英文
hardware multiplication
  • 硬 : 形容詞1 （堅硬） hard; stiff; tough 2 （剛強; 堅定; 強硬） strong; firm; tough; obstinate 3 （勉...
  • 體 : 體構詞成分。
  • 法 : Ⅰ名詞1 （由國家制定或認可的行為規則的總稱） law 2 （方法; 方式） way; method; mode; means 3 （標...
  • 硬體 : hardware
  1. In addition, many other problems also exist in hardware neural network, including error problem, learning mode, parallel architecture, and also neural network inner linking problem, hidden layer and the realization of the multiplicator and etc. for instance, error problem : hardware neural network employs the limited precision, and will inevitably bring limited precision error

    另外，硬體實現神經網路還存在誤差問題，學習方式，并行結構等方面的問題，還有神經網路內部的連接問題，隱層及乘法器的實現等等。如誤差問題，硬體實現神經網路使用的是有限精度，不可避免的會產生有限精度誤差，選取合適的精度，才能既適合空間的要求，又避免對網路的實現產生一定的影響。
  2. We select ni / cr alloy resistor as element together with ceramic embedding hearth ; select small flat - and - disc heat - even hubby ceramic sample holder, select ni / cr & ni / si thermoelectric couple ( type k ) as thermoscope with threads 0. 5 mm in diameter which is installed in the middle of the holders symmetrically ; select aluminum silicate fire - retardant fiber as materials for heat preservation ; design some hardware, for example temperature controller & transporter, signal amplifier etc ; design controlling curve to heat stove ; and introduce the method of least squares nonlinear regression and subsection function to deal with data. in order to obtain the reasonable operation conditions and operation curve, we have also done many theory analysis and experiment discussions

    通過理論和試驗探討，選用鎳鉻合金電阻絲作為加熱元件，配以陶瓷質埋入式爐膛；選用陶瓷質小尺寸扁平?圓盤均熱塊體型樣品支持器；選用0 . 5mm絲徑鎳鉻?鎳硅熱電偶（ k ）作為測溫元件；熱電偶對稱安置在樣品支持器容器的中部；選用硅酸鋁耐火纖維作保溫材料；合理選用和設計了溫度控制器、溫度變送器、信號放大電路等硬體；採用升溫曲線來控制爐膛供熱過程；採用最小二乘法非線性回歸與分段函數相結合的曲線模擬方法，進行圖形處理。
  3. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  4. After that, it gives the measures of designing dsp ' s assembler as a part of the dsp ' s software development environment together with the c - compiler. moreover, this paper explores the method of design the floating - point arithmetic unit. referring to the ieee754 - 1985 standard for binary floating - point arithmetic, the algorithm and the behavior description of floating - point adder and multiplier is given, and the simulation and verification is shown at the end of this paper

    此外，本文還對處理器的浮點運算單元設計做了初步的研究，以ansi ieee - 754浮點數二進制標準為參考，借鑒了經典的定點加法器和乘法器的設計，嘗試性的給出了浮點加法單元和乘法單元的實現模型和行為級上的硬體描述，並對其進行模擬和驗證。
  5. The subject inducts digital time division technology ( pwm ), which is more advantageous at the accuracy and the predigest of hardware than simulant multiplication. what they call measuring power energy reasonably is that measuting except harmonics power energy fed back power. yet it realizes reasonable measurement of power energy which measures by base wave ac parameters method base on digital time division

    本課題引入了數字時分割（ pwm ）脈寬調制技術，在測量的準確性、硬體電路的簡化等方面都比模擬乘法器具有較高的優越性。所謂合理的計量電能，就是不計非線性負載回饋給電網的負的諧波電能，而採用基於數字時分割的基波交流參數測量的方法，真正實現了電能的合理計量。
  6. Different from general microprocessors, dsps have harvard architecture or enhanced harvard architecture and units of dsps can work in parallel. to perform multiplication in high speed, dsps also include hardware multiplier in its cpu

    與通用微處理器不同，數字信號處理器採用了哈佛總線結構或改進哈佛總線結構，具有高度的并行性，為了快速完成乘法計算在cpu中增設了硬體乘法單元。
  7. It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ), 5 - stage pipeline, hardware multiplier and divider, interrupt controller, 16 - bit i / o port and a flexible memory controller. new modules can easily be added using the on - chip amba ahb / apb buses. it has flexible peripheral interfaces, so can be used as an independent processor in the board - level application or as a core in the asic design

    它遵照ieee - 1745 （ sparcv8 ）的結構，針對嵌入式應用具有以下特點：採用分離的指令和數據cache （哈佛結構） ，五級流水，硬體乘法器和除法器，中斷控制器， 16位的i / o埠和靈活的內存控制器，具有較強的異常處理功能，新模塊可以輕松的通過片上的ambaahb / apb總線添加。
  8. The inversionless bm algorithm in rs decoder is implemented with serial mode, which avoids the inversion computation and only needs 3 finite - field multipliers. thus, the complexity of hardware implementation has been mostly reduced. a 3 - level pipe - line processing architecture is also used in the hardware and the coding circuit in rs coder is optimized by using the characteristics of the finite - field constant multiplier

    Rs解碼器的設計採用無逆bm演算法，並利用串列方式來實現，不僅避免了求逆運算，而且只需用3個有限域乘法器就可以實現，大大的降低了硬體實現的復雜度，並且因為在硬體實現上，採用了3級流水線（ pipe - line ）的處理結構。
  9. The high speed mcu c8051f120 includes a multiply and accumulate engine ( mac ) which can be used to speed up mathematical operations, design control, display circuit and process data

    選用高性能單片機c8051f120 ，利用其帶有硬體乘法器、運行速度高等優點，設計控制及顯示電路，進行數據處理。
  10. This article provides a brief description of rsa public key cryptography, an analysis and compare of all kinds of present existed modular exponentiation in rsa public key cryptography, a colligation of the fastest accelerating software algorithm - vlnw sliding window methods and hardware mapping fast montgomery modular multiplication algorithm that can improve the implementary efficiency of rsa public key cryptography for achieving the novel algorithm - mnexp algorithm

    本文簡單介紹了rsa公鑰密碼體制，分析比較rsa公鑰密碼中已有的模冪運算方法，將得到的最快軟體加速演算法vlnw滑動窗口法和硬體映射最快的montgomery模乘演算法綜合，得到改進后的mnexp演算法能有效提高rsa公鑰密碼的實現效率。橢圓曲線密碼系統被認為可以替代rsa演算法的一種公鑰密碼體制。
  11. So, the emphases are put on this part. first, all sources of noise are analyzed and calculated to determine the parameter of component and estimate the feasibility of the system. second, on the one hand, low noise wideband and high gain amplifier is detailed particularly in the design of hardware, on the other hand, several mathematical methods are introduced to reduce the noise further in the design of software

    首先，詳細分析了整個系統的噪聲來源，計算可能出現的噪聲，在器件的選擇上對參數提出要求，並分析方案的可行性；其次，在硬體設計上，兼顧帶寬，噪聲與放大倍數；在軟體設計上，採用累加平均，最小二乘擬合等信號處理方法，進一步降低噪聲。
  12. Those compressions algorithms are suited to implementation by hardware and have good realtime quality because they do n ' t have multiplication and division operation. those algorithms can achieve c ompression ration over 10 to 1 at the same time of keeping all the important detecting correlative data by using lossless method to compress important data and using lossy method to compress insignificant data

    壓縮演算法中不使用乘除法運算，非常適合於硬體實現並具有很好的實時性；通過對重要數據和非重要數據分別進行無損壓縮和有損壓縮，演算法在保留所有檢測相關數據的基礎上可以達到10 ： 1以上的壓縮比。
  13. The method of using microcontroller and multiplicative d / a transformer to simulate the signal of resolving - transformers and its hardware implement are introduced

    本文介紹了用單片機及乘法型d a轉換器模擬旋轉變壓器信號的方法及硬體實現技術。
  14. In this dissertation, the method to design and realize the digital receiver in the field programmable gate array ( fpga ) has been discussed ; combining coordinate rotation digital compute ( cordic ) to design nco, we get a efficient structure without multiplications

    本論文正是運用現場可編成邏輯器件（ fpga ）設計與實現數字接收機問題開展研究，結合坐標旋轉數值計算（ cordic ）演算法實現數控振蕩器（ nco ） ，得到一種免乘法器高效可移植性好的數字接收機fpga實現結構，並在現有的硬體平臺上進行了接收機系統的調試，測試結果表明該接收機能夠達到系統指標要求。
  15. A number of challenges needed to be met to design and implement a jpeg coding in hardware rather than in software running on a microprocessor. jpeg coding normally requires many floating - point multiplication calculations

    Jpeg需要進行大量的浮點乘法運算，但用硬體實現乘法運算會佔用比實現加法運算多得多的晶元資源。
  16. In addition, the paper presents filter multi - phase structure for the shaping - filter design and its fpga implementation, where multipliers can be omitted by using the look - up table of the filter coefficients rom. test of the prototype circuit board shows the method is perfect

    然後介紹了數字成形濾波器多相結構的fpga實現方法，運用查詢系數rom的方法可以省去實現濾波器的乘法器結構，並對此實現方法進行軟體模擬和硬體電路板測試，測試結果達到了較理想的效果。
  17. This paper introduces modern test and fault diagnosis methods and then discusses common principle and method for design of its hardware, software and interface with the background study on lawn mower

    本文首先對現代檢測與故障診斷方法進行了綜述，以某廠生產的駕乘式割草機、掃雪機變速箱為背景，論述了檢測診斷系統硬體、軟體、介面設計的一般原理和方法。
  18. It was the second death in less than a year related to the epcot center ride mission : space, which spins riders in a centrifuge that subjects them to twice the normal force of gravity

    去年6月，一名來自賓夕法尼亞州的4歲男孩與母親和姐姐在乘坐「太空飛船」的過程中出現身體僵硬，四肢崩緊的征狀。
  19. As a special element to process digital signal, the basic theory of dsp was studies internationally in 1960s, and the first general dsp chip, with a hard multiplier, was put out in 1980s

    Dsp （ digitalsignalprocessor ）是一種專用的數字信號處理器。 20世紀60年代國際上開始了dsp理論基礎研究， 80年代推出第一個具有硬體乘法器的通用dsp晶元。
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