累加器 的英文怎麼說

中文拼音 [lěijiāqì]
累加器 英文
acc accelerator
  • 累 : 累Ⅰ形容詞（疲勞） tired; fatigued; weary Ⅱ動詞1. （使疲勞; 使勞累） tire out; wear out 2. （操勞） work hard; toil
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 累加 : accumulation; cumulation; summation累加器 [自動化] accumulator carriage; accumulator register; ac...
  1. This moves the carry into bit position of the accumulator.

    把進位移到累加器的位元。
  2. To form the results of an operation in an accumulator

    在累加器中形成運算結果。
  3. Adat automatic data accumulator and transfer

    自動數據累加器與傳輸
  4. The counter has been preset to 0000 and as the input "runs, " the counter advances by 1 bit per input pulse.

    計數器預置0000，並在時鐘輸入下計算每輸入一個脈沖計數器便累加10。
  5. The signal totalizer integrator can be used to compute a time - input product

    信號累加器積分器用於計算時間輸入產品。
  6. The totalizers are turned one by one and then ” snailed ” ( decorated with spiral lines ), before being colored

    用車床將累計器一個個加工出來，然後飾配用螺旋紋狀線條，最後再進行著色。
  7. This can be used to provide readout of totalized flow, calculate service intervals of motors or pumps, etc. the totalizer can also accumulate batch weighing operations

    它可以讀出總電流計算馬達或泵的運行間隔等等。累加器也可以累計成批稱重操作。
  8. This article deals with the method to determine the guard digit in the left normatlization of float point number in the analysis and design of computer system, and briefly introduces its application in practice

    摘要介紹了在計算機系統分析和設計中，用於浮點數左規格化的警戒位的設置方法，並簡要說明了該類警戒位與用於舍入的警戒位共同組成了運算器中的累加器的實際警戒位字長。
  9. Combining the principles of pipelining and parallelism of dsp with idct theory, we concentrate on the use of multiply - accumulate unit of mcf5272 by merging the operations of addition and multiplication, and realize two dimension of idct with one dimension of idct efficiently. testing shows the software meets the requirement of real - time decoder

    重點結合mcf5272的流水線操作和并行操作特徵和反離散餘弦變換演算法原理，將的二維反離散餘弦變換轉換成8點的一維反離散餘弦變換，利用乘法累加器合併加法運算和乘法運算高效快速地實現了反離散餘弦變換演算法。
  10. All instructions are carried out using a register called the accumulator, which we shall denote by a.

    全部指令執行時都用了稱作累加器的寄存器（用符號A來表示）。
  11. Optimal design for phase accumulater of dds based on verilog hdl

    相位累加器的一種優化設計
  12. Accumulator and index register can be accessed by the programmer

    程序員可以對累加器和變址寄存器進行存取。
  13. Accumulator transfer instruction

    累加器轉移指令
  14. Accumulator shift instruction

    累加器移位指令
  15. Chapter five discusses the design and the process of the generation of the control function, including counter, accumulator, comparator, shift register, demultiplexer, collector, access record. chapter six gives some advice and opinions on how to improve this computer software

    其次介紹了計數器、累加器、比較器、多路輸出選擇、移位寄存器控制項；數據類中的收集器、訪問記錄/部分輸出記錄等控制項的功能介紹和編程思路以及使用實例第六章對平臺的完善和改進闡述了一些個人的建議和想法。
  16. The model, in this case, is the high - level language program - which, like all useful models, hides irrelevant detail about the idiosyncrasies of the underlying computing technology such as internal word size, the numbers of accumulators and index registers, the type of alu, and so on

    這種情況下，模式就是這個高級語言程序，它就像所有有用的模式那樣，隱藏了潛在的計算技術特性上的相關細節（比如內存字元大小，累加器的個數，索引寄存器， alu算術邏輯單元類型等等） 。
  17. The direct digital frequency synthesizer is a kind of fully digitized frequency synthesizer, which consists of the phase accumulator, the sine look - up table, the digital to analog converter and the low band filter. it is of high frequency resolution, fast frequency switching speed, low phase noise, the ability to switch frequencies while maintaining constant phase, and the ability to producing arbitrary waveforms

    直接數字頻率合成器是一種全數字化的頻率合成器，由相位累加器、波形rom 、 d a轉換器和低通濾波器構成， dds技術具有頻率解析度高、頻率切換速度快、頻率切換時相位連續、輸出相位噪聲低和可以產生任意波形等優點。
  18. 2. with a view to the theory of dds, this paper introduces the realization of dds, which based on programmable device. it also discusses in detail some key techniques such as the design of high speed phase accumulator and ram

    2 .從dds的原理出發，著重介紹了一種自行設計的基於可編程邏輯器件fpga的dds電路的實現方法，並對其高速相位累加器、 ram查找表等關鍵技術進行了詳細討論。
  19. All instructions are carried out using a register called the accumulator, which we shall denote by a

    全部指令執行時都用了稱作累加器的寄存器（用符號a來表示） 。
  20. This dissertation refers to several typical examples of existing multipliers and accomplishes a specific multiplier, which can meet the performance requirement of t2181 processor. the designs of flexible power management, powerful serial ports and memory architecture are also included in this dissertation

    乘累加器中的乘法器是影響系統性能的關鍵數據路徑，本文參考了現有的幾種典型乘法器結構，針對t2181dsp處理器的性能要求，提出了乘法器的改進結構，在此基礎上實現了高性能的乘累加器，為系統整體性能的提高奠定了基礎。
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