譯碼存儲器 的英文怎麼說

中文拼音 [yìmǎcúnchǔqì]
譯碼存儲器 英文
translation memory
  • 譯 : 動詞（翻譯） translate; interpret
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 存 : 動詞1 （存在; 生存） exist; live; survive 2 （儲存; 保存） store; keep 3 （蓄積; 聚集） accumulat...
  • 儲 : Ⅰ動詞（儲藏; 存放） store up; save; keep [have] in reserve Ⅱ名詞1. （繼承人） heir 2. （姓氏） a surname
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 存儲 : [計算機] memorizing; storage; memory; store
  1. The number of error symbols that can be corrected by the decoder is 2. the design process includes storing the input data, calculating the syndromes, designing multiplier and divider and solving the key equation

    Rs （ 256 ， 252 ）譯碼器的設計過程主要包括輸入數據的存儲、伴隨式的計算、乘法器和除法器的設計、關鍵方程的求解等幾個步驟。
  2. Random access memory is used to store dynamic data structures and jit - compiled code

    隨機訪問存儲器（ ram ）用於存儲動態數據結構和jit編譯的代碼。
  3. In the part, there are following contents : single - chip and memory circuit, interrupt control circuit, decoding circuit, parameter area circuit, watchdog circuit and serial communication interface circuit, etc. in this paper, serial communication interfaces between upper pc and lower single - chips are designed

    其中，微處理器的設計是關鍵。在微處理器部分的設計中，主要包括以下內容：單片機及存儲器電路設計、譯碼器電路設計、參數區電路設計、中斷控制電路設計、看門狗電路設計、串列通信介面電路設計等。
  4. The whole circuit includes memory array, decode, sense amplifier, data in - out circuit and pre - charge circuit

    電路包括存儲陣列、譯碼電路、敏感放大器、數據輸入輸出電路，預充電電路等部分。
  5. The compiler can store this directive in its symbol table and use it during the intermediate code generation phase

    編譯器可以將這個指示符存儲在它的符號表中，並在中間代碼生成階段使用這個指示符。
  6. The circuit design mainly includes interface designs, such as address coding circuit, memory, human - machine, ad converter, the power, etc. the pcb was protracted and tested

    電路設計主要包括譯碼電路設計、存儲器介面電路設計、人機介面電路設計、 ad轉換器電路設計、數控恆流源介面設計等。
  7. The hardware system includes power supply circuit, clock reset circuit, jtag model building circuit, decoding circuit, memory interface circuit, man - machine interface circuit and numeric control constant - current source interface circuit

    硬體系統主要包括電源電路、時鐘復位電路、 jtag模擬介面電路，譯碼電路、存儲器介面電路、人機介面電路、 adc轉換電路和數控恆流源介面等。
  8. Since this decoder has high error - correcting speed and regular structure, it may apply to data transmission and storage to decrease error rate

    由於該譯碼器有較高的糾錯速率和規則的設計結構，使它可以方便地用於數據傳輸和存儲過程中進行差錯控制。
  9. The vd is composed of four functional units : 1 ) the branch metrics unit ( bmu ) ; 2 ) the add - compare - select unit ( acs ) ; 3 ) the path metrics unit ( pmu ) ; 4 ) the survivor memory unit ( smu ) ; regarding the power dissipation of the viterbi decoder, the smu is the hottest spot in the viterbi decoder due to the frequent memory accesses. there are two traditional techniques for the realization of survivor memory unit in viterbi decoder - - register exchange ( re ) and trace back ( tb ) method

    這是當前開展低功耗邏輯優化的重要方面，也是本課題採用的方法。 viterbi譯碼器主要由四個功能單元組成:分支度量單元（ bmu ） ，加比選單元（ acs ） ，路徑度量存儲單元（ pmu ） ，倖存路徑存儲和輸出單元（ smu ） 。本文所做的viterbi譯碼器設計採用模塊化的設計方法，先對各個功能單元進行優化設計，然後將各個功能單元組合在一起，形成最終的譯碼器。
  10. Some new technologies such as dividing the memory array into separated sub - arrays, atd, pre - charge and balance, subsection decoding, multilevel sense amplifier, etc have been used

    設計中採用了諸如存儲陣列分塊技術，地址探測技術，預充電及平衡技術，分段譯碼技術，分級敏感放大器等一些新技術。
  11. Re has a very complicated interconnections and needs a high power consumption. tb needs a large quantity of buffers and has long decoding delay. in this paper a modified register - exchange ( re ) method is presented, which reduce its memory access rate and its amount of memory, thus, reduces the power consumption

    在smu中，由於要進行頻繁的存儲器讀寫，功耗很大，成為整個viterbi譯碼器中消耗功率最大的單元，因此對smu單元進行低功耗設計對降低viterbi譯碼器的功耗起著非常重要的作用。
  12. Abstract : at first, this paper analyces the open defect of cmos ram address decoder, it comes out that one type open defect cannot be detected by march test algorithm, and then we give the test method of this type undetectable fault and the design scheme with built - in tolerance against hard - to - detect open defects

    文摘:對cmos存儲器中地址譯碼器的開路故障進行了分析和分類，得出了其中有一類開路故障不能用常用的測試演算法可靠的測試出，給出了測試該類開路故障的測試方法以及針對該類開路故障的容錯性設計方案。
  13. Then, memory cell array and some parts of peripheral circuits used in sram, for example, sense amplifyier and adderss decoder, are designed and verifyied by simulation. furthermore, some novel methods, such as clocked hierarchical word decoding structure, multi - stage sense amplifyier, common data line and data bus equlibruim technology has been applied in the design of 128kbit and imbit sram. what ' s more, we have studied compiler technology applied in the designing course of a imbit full cmos sram from the pointview of methology

    然後對sram的存儲單元電路以及外圍電路中的靈敏放大器和地址譯碼器進行了設計和模擬，在此基礎上，以128kb和1mb全cmossram設計為例，從方法學角度對同步sram設計中的帶時鐘分等級字線譯碼，多級靈敏放大和位線及總線平衡等技術進行了研究，並給出了相應的compiler演算法。
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