邏輯介面單元 的英文怎麼說
中文拼音 [luójièmiàndānyuán]
邏輯介面單元
英文
logic interface unit-
By thorough analysis and synthetize this paper made a frame of the system of intelligent instrument and its hardware structure. as followed, this paper depicted design details of intelligent instrument " s hardware, it included the design of interface circuit, data commutations and digital logic of dsp, mcu, internet ' s chip and isp ' s apparatus etc., and have designed schematic map and circuit. so it accomplished the full design of hardware / software of the new type intelligent instrument
本文具體給出了新型智能儀器硬體結構及實現，描述了智能儀器硬體設計細節，包括數字信號處理器、單片機、 internet接入晶元、可編程數字/模擬器件等在新型智能儀器中的介面電路設計、數據通信設計和數字邏輯設計等，詳細地給出了設計原理圖和電路圖；給出了新型智能儀器的軟體設計細節，從而完成了新型智能儀器完整的軟硬體設計。With turning the scale of asic ( appl ication specified integrated circuits ) to s0c ( system on chip ), which conunon1y is composed of mcu, specified function ip cores, memory, periphery interface etc, the ip reuse techno1ogy is very important in s0c design flow, which can realize the constructions of different levels components. the approach of configurable system, method and design f1ow for udsm ( u1tra deep sub micron ) asic, logic system design using hdl 1anguage, coding style, static and dynamic verification strategy are a1so presented in chapter 2. in chapter 3 we study the vlsi - - dsp architecture design, dense computation and high speed high performance digital signal processing unit structure, which includes high speed mac components and distributed arithmetic unit
在工程設計方法及結構化設計和高層次綜合的研究中，介紹了在深亞微米工藝條件使用的方法和asic設計流程，討論了高層次綜合的核心如何從描述推出電路構成的設計思路，針對不同目標的設計技巧討論了採用hdl語言進行邏輯系統設計的方法，給出了用vhdl語言進行代碼設計時的規范和風格，在面向soc的驗證策略討論了動態和靜態的驗證技術，提出了進行單獨模塊驗證、晶元的全功能驗證和系統軟硬體協同驗證的整體策略。As we saw earlier in the section on linux and segmentation, each segment descriptor uses same set of addresses for linear addressing, minimizing the need to use the segmentation unit to convert logical addresses to linear addresses
前面介紹linux分段模型時已提到，每個分段描述符都使用相同的地址集進行線性尋址，從而盡可能降低使用分段單元將邏輯地址轉換成線性地址的需要。Concretely, on the basis of describing the communication specification of arinc 429 with enhanced parallel port ( epp ), the standard and the module application of dsp and cpld, the thesis has proposed the design of the arinc 429 technology based on dsp system. at first, the function and the application of each module of the system and the operation principle of high - performance cmos bus interface circuit hs - 3282 chip which forms the main body of the data diversion of the interface module are introduced. secondly, the hardware structure of the interface module is described in detail, mainly including data latch and buffer circuit, choice circuit of transmission rate, etc. and then the design philosophy and flow charts of the software are fully discussed, such as the basic requirement of software, the design and realization of the function
本文在簡單的論述了pc並口協議（ epp ）與dsp之間的通信方法、 cpld模塊邏輯控制應用和arinc429的通訊規范的基礎上，給出了基於dsp的arinc429通訊介面的設計方案:對通訊板中各模塊的功能和應用以及構成數據轉換主體的總線介面晶元hs - 3282的工作原理做了說明;介紹了本設計所用的dsp和cpld的功能概況;詳細敘述了通訊板介面模塊的硬體結構設計，其中，對數據緩沖電路、數據傳輸速率選擇電路、邏輯控制電路等各關鍵點做了重點介紹;具體闡述了軟體設計思想及流程圖，包括軟體的基本要求和功能的設計與實現;接著從埠譯碼單元、 i / o通道、電平轉換電路等方面進行了介面模塊的軟、硬體調試;最後，給出了測試結果，對研製工作做了總結，對本設計的優缺點各做了評述。With the exist of fpga chip ep1k30tc144 - 3, several hardware functions are realized in the chip, such as sample controlling logic, fifo inside, the connection circuit with pc, the connection circuit with mpu, the connection circuit with keyboard
系統採用了fpga晶元ep1k30tc144 - 3 ，並且在晶元內集成了采樣控制邏輯，內置hfo ，上位機介面，單片機介面以及鍵盤介面等多個功能模塊，使得數據採集卡的結構大大簡化。Circuit design is the basis of design of demultiplexer. speed, power and chip area are the main factors that should be considered in circuit design. every circuit structure has its merits and drawbacks, e. g. cmos logic family has a slower speed, but lower power, smaller area, scfl ( source couple fet logic ) family has a higher speed, but higher power, larger area. we should choose a proper circuit structure or their mixed structure for certain design to get a good tradeoff among the three factors. flip - flop is the fundamental element of demultiplexer, setup time and hold up time are key factors, which influence the speed of circuit, thus the design aim is how to reduce them. in this thesis we place emphasis on the design of scfl latches
速度、功耗、面積是電路設計要考慮的主要因素，不同的電路形式具有不同的優缺點，如cmos互補邏輯電路功耗低，面積小，速度相對較慢； scfl （源極耦合fet邏輯）電路速度高，功耗和面積較大。所以要針對具體設計需要選用適當的電路形式或其組合結構，以滿足設計要求。觸發器是分接器的基本組成單元，建立時間和保持時間是影響電路速度的關鍵，所以減小建立時間和保持時間是觸發器設計的主要目標，本文著重介紹了scfl鎖存器的設計和優化方法。In this article, we firstly analyze the present status of cbse mainly concerning its framework. some deficiencies are pointed out as follows : some present component frameworks focus on the service providing for the components, but the separation of interface layer and business logic layer is ignored ; components are tightly coupled with the api provided by the framework ; lacking the support for component unit testing ; lacking the support for the modularization of crossing cutting concerns
本文首先以cbse中的框架為切入點，分析了cbse的現狀，並指出了其中一些不足之處：現有的一些構件框架僅僅強調給構件提供服務，而忽略了介面層和業務邏輯層的分離；構件依賴于特定框架的api ；缺乏對單元測試的支持；缺乏對橫切關注點（ crosscuttingconcerns ）的模塊化支持。Offer the bridge and tie of the information transmission between picture gather and pretreatment unit and many dsp parallel structure goal discerning unit. there is a mapping transformation from picture data source logic to host interface ( hip ) logic, and considers the conversion between 5v logic and 3v logic
提供了圖像採集及預處理單元與多dsp并行結構目標識別單元進行信息傳遞的橋梁和紐帶，將圖像數據源邏輯映射成主機介面（ hpi ）邏輯，同時考慮了5v邏輯和3v邏輯間的轉換問題。This design uses the solution of fpga and pci core instead of regular cpci interface chip. this paper introduces one easy but efficient design method of pci interface through using pci core
摒棄常規cpci介面晶元，採用fpga + pcicore的方案：本文使用pci核邏輯的簡單高效的pci介面設計方法。分享友人