邏輯單元組 的英文怎麼說

中文拼音 [luódānyuánzǔ]
邏輯單元組 英文
group of logical units
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 組 : Ⅰ名詞1 （由不多的人員組成的單位） group 2 （姓氏） a surname Ⅱ動詞（組織） organize; form Ⅲ量詞（...
  • 邏輯 : logic
  1. We proposed an order - oriented shop floor control model, which is based on mas and dynamic _ logical cell to overcome the weakness of the existing distributed and hierarchical form. the model is divided into three layers, namely the shop floor layer, the dynamic cell layer and the equipment layer. the tasks of shop floor layer are to receive, decompose and administrate orders

    論文分析了製造系統控制結構發展演變的過程，針對分散式控制方式及傳統分層遞階控制方式的不足，提出了面向訂單的、基於多agent和動態邏輯單元的車間控制模型，該模型根據車間生產組織的特點將agent劃分為三層，即車間層、動態單元層和設備層。
  2. Application of the pre - feed coal control logic in ccs of power generation unit

    預給煤控制邏輯在單元機組協調控制系統中的應用
  3. Mode, ext3 only officially journals metadata, but it logically groups metadata and data blocks into a single unit called a transaction

    方式下， ext3隻是正式記錄元數據，而在邏輯上將元數據和數據塊分組到稱為事務的單個單元中。
  4. In this course, we study low - power computer design techniques involving mos circuits, logics, computer organization, function units, pipeline, bus protocols, memory subsystems, compiler, os, and virtual machines

    本課程中，我們將研讀計算機低功耗設計技術，內容涵蓋mos電路，邏輯，計算機組織，功能單元，管線處理，匯流排規約，記憶體子系統，編譯器，作業系統，及虛擬機等的相關設計。
  5. Metadata registry of cv enable automatic information discovery. thesautus item unit the information granularity to integrate data, protocol and logistic in the web service framework

    Webservice框架下受控語言採用詞匯信息單元作為信息粒度，提供建立包括數據、協議和應用邏輯在內的組件方式集成應用系統。
  6. " the content of the news website edit " is the main research range of this thesis, according to the elementary cells of websites and basic institutional framework, viz. point - information, webpages element, line - namely its interrelation, plane - the layout of the webpages, body - website ' s logic structure and whole style, analysis it from these four respects mentioned above

    本文針對網站的「情境編輯」為主要研究范圍，按照網站的基本單元和基本組織結構，即：點? ?信息、網頁元素；線? ?即其相互關系；面? ?網頁版面；體? ?網站邏輯結構和整體風格，從這四個方面對其加以逐層分析。
  7. Determines the logical unit of work that the component s processing executes

    -確定組件處理執行的邏輯工作單元。
  8. A multiphase process that copies all the data and log pages from a specified backup to a specified database the data - copy phase and rolls forward all the transactions that are logged in the backup the redo phase

    事務（ transaction ）組合成一個邏輯工作單元的一組數據庫操作，這些操作要麼全部提交，要麼回滾。事務是原子的、一致的、孤立的和持久的。
  9. Clauses can be grouped to operate as a single unit separate from the rest of the query ; like putting parentheses around an expression in a mathematical equation or logic statement

    可以對子句進行分組，使其作為獨立於查詢的其餘部分的一個單元來工作，這類似於在數學等式或邏輯語句中的表達式兩側加上括號。
  10. Query clauses can be grouped to operate as a single unit separate from the rest of the query, similar to putting parentheses around an expression in a mathematical equation or logic statement. when you group clauses, the

    可以對查詢子句進行分組，使其作為獨立於查詢的其餘部分的一個單元來工作，這類似於在數學等式或邏輯語句中的某個表達式兩側加上括號。
  11. The paper analyses its key circuit and software program structure. this full - digital controller is made up of dsp and implements single neuron adaptive pid computation, current pi computation, logical determination, pulse - fire and procession of protective signal etc. it also improves the reliability and availability of this control system

    本課題對控制器主要的電路結構及程序結構進行了分析，以dsp為核心組成的全數字式控制器完成了電流pi演算法計算，單神經元自適應pid演算法計算、邏輯判斷、脈沖觸發以及系統保護信號的處理等，提高了控制器的可靠性和可操作性。
  12. Circuit design is the basis of design of demultiplexer. speed, power and chip area are the main factors that should be considered in circuit design. every circuit structure has its merits and drawbacks, e. g. cmos logic family has a slower speed, but lower power, smaller area, scfl ( source couple fet logic ) family has a higher speed, but higher power, larger area. we should choose a proper circuit structure or their mixed structure for certain design to get a good tradeoff among the three factors. flip - flop is the fundamental element of demultiplexer, setup time and hold up time are key factors, which influence the speed of circuit, thus the design aim is how to reduce them. in this thesis we place emphasis on the design of scfl latches

    速度、功耗、面積是電路設計要考慮的主要因素，不同的電路形式具有不同的優缺點，如cmos互補邏輯電路功耗低，面積小，速度相對較慢； scfl （源極耦合fet邏輯）電路速度高，功耗和面積較大。所以要針對具體設計需要選用適當的電路形式或其組合結構，以滿足設計要求。觸發器是分接器的基本組成單元，建立時間和保持時間是影響電路速度的關鍵，所以減小建立時間和保持時間是觸發器設計的主要目標，本文著重介紹了scfl鎖存器的設計和優化方法。
  13. The control system includes two modules, one named the input module which acquires data digitally, and the other, named the output module, controls the emission of the laser, the gating function of the single photon counting module ( spcm ) and the synchronization of the input and output modules. each of them uses a complex programmable logic device ( cpld ) as the core component, and is devided into three parts : the hardware circuit, the programming logic circuit and the software

    該控制系統主要包括控制單光子發射、單光子探測器、數據採集接收系統的輸出系統和數據採集系統兩個模塊，它們都採用復雜可編程邏輯器件cpld作為核心功能晶元，由硬體電路設計、晶元編程和高級軟體編程三部分組成。
  14. Alternatively, you can think of a single porttype element as a logical grouping of methods into classes

    。或者，您也可以將單個porttype元素看作是將各種方法組成類的一個邏輯分組。
  15. The vd is composed of four functional units : 1 ) the branch metrics unit ( bmu ) ; 2 ) the add - compare - select unit ( acs ) ; 3 ) the path metrics unit ( pmu ) ; 4 ) the survivor memory unit ( smu ) ; regarding the power dissipation of the viterbi decoder, the smu is the hottest spot in the viterbi decoder due to the frequent memory accesses. there are two traditional techniques for the realization of survivor memory unit in viterbi decoder - - register exchange ( re ) and trace back ( tb ) method

    這是當前開展低功耗邏輯優化的重要方面，也是本課題採用的方法。 viterbi譯碼器主要由四個功能單元組成:分支度量單元（ bmu ） ，加比選單元（ acs ） ，路徑度量存儲單元（ pmu ） ，倖存路徑存儲和輸出單元（ smu ） 。本文所做的viterbi譯碼器設計採用模塊化的設計方法，先對各個功能單元進行優化設計，然後將各個功能單元組合在一起，形成最終的譯碼器。
  16. Sets of memory bits in the “ basement ” of the chip customize each cell so that it performs a particular logical function

    晶片底層的記憶位元組可依特定需求製造每個單元，使各單元能夠執行特定的邏輯功能。
  17. A temporal logic is normally built atop a simpler set of atomic small - unit propositions, such as traditional program assertions

    ）通常，時態邏輯構建於一組更簡單的原子（小單元）命題之上，如傳統程序斷言。
  18. Hence, the advantage of mtn over stn was shown with the facts that the nns need fewer neurons by using mtns than by using stns. in addition, the literal, and, or operation as three basic operations in ternary logic were separately implemented by single mtn. with these basic mtns, arbitrary ternary function can be achieved by nns

    利用這一方法，用一個多閾值神經元即實現了需三個單閾值神經元方能實現的異或運算，由此大幅減少了神經元個數；用一個多閾值神經元分別實現了三值邏輯中的文字、與、或三種基本運算，由這三種基本運算的多閾值神經元，可組成實現任意三值函數的多閾值神經元網路，由於提高了單個神經元信息處理的能力，使神經網路可實現復雜的多值邏輯，性能得以提高。
  19. In this type manufacturing resources are organized by group technology ; another type of cell is organized by machine tool cluster. according to the principle and methodology proposed in this thesis, regardless of its cell, any resource can be integrated in to our dynamic _ logical cells owning to the application of network and mas technology, thus displaying great advantage in improving dynamic reconfiguration and resource sharing at shop floor

    按照本文的原理和方法，任何一個資源都可以參與到需要的動態邏輯單元中，不受所屬的物理單元的限制，從而把基於成組製造單元和基於機群這兩種完全不同的車間組織形式，通過網路化和agent技術從邏輯上統一起來，充分發揮兩者的優點，提高車間動態重構和資源共享的能力。
分享友人
分享到 Line

分享到臉書