邏輯電路組 的英文怎麼說

中文拼音 [luódiànlùzǔ]
邏輯電路組 英文
hard-wired logic
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 組 : Ⅰ名詞1 （由不多的人員組成的單位） group 2 （姓氏） a surname Ⅱ動詞（組織） organize; form Ⅲ量詞（...
  • 邏輯 : logic
  • 電路 : [訊] circuit （ckt）; electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...
  1. These character based on sichuan power network ' s practice operation experience, in allusion to the config of the carrier wave protection in bypass breaker operating, through the study of protection ' s typical config : one side lfp - 902a, one side csl - 101a, proceeded comprehensive act module test, noted plenty of first hand test data and wave picture, proceeded detailed theory analyses, plenitude demonstration atresic type carrier wave distance protection when twain side atresic type logic is not completely same, basically can fill power network ' s requirement to relay of reliability selectivity speedly and sensitively

    本文結合四川電網的實際運行經驗，針對旁路開關代路運行時的保護配置情況，通過對旁路代路時保護典型配對組合：一側lfp - 902a ，一側csl - 101a的保護配置情況的深入研究，做了全面的動模試驗，記錄了大量的第一手試驗數據和波形，進行了詳細的原理分析，充分驗證了高頻閉鎖式距離零序保護在兩側閉鎖式邏輯不盡一致的情況下，基本能夠滿足電網對繼電保護的可靠性、選擇性、快速性以及靈敏性的要求。
  2. Through the simulation of large - scale circuit simulation proved that use the crossover tearing technology could detailed network structure, simplify the diagnostic process, and the neural network can parallel deal with the diagnosis information, and the logic operation can judge the information of the multi - fault. the illustrative simulation shows that it can increase the diagnosis speed and decrease the workload before test

    通過對大規模模擬電路的模擬證明，使用交叉撕裂明細網路結構，簡化診斷過程，且運用神經網路組對信息進行并行處理，邏輯分析運算對多故障信息進行處理判斷，大大提高了故障診斷速度，減小了測前工作量。
  3. It can give bdd presentation of boolean function or arbitrary combination logic circuits which are presented by cdl, and can realize different operation of boolean function by the operation to bdd

    能完成對任意基於cdl語言描述的組合邏輯電路或布爾函數，實現其bdd表示並通過對bdd的操作實現對相應組合電路或布爾函數的操作。
  4. Secondly, the composition and function of expander board is introduced, the paper describes a detail developing process of selecting component, design interface circuit, protract pcb with protel and design pci interface logic and user ' s logic. with ahdl and max + plus. in addition this paper discusses how to debug pci board, and give the simulation waveform and the result of debug. on the base of all functions is ture, this paper introduce the config registers and memory of bu - 61580, realize the interrupt function and communication based on mil - std - 1553b

    首先分析了擴展板的組成、功能，對pci介面邏輯和擴展板的內部邏輯進行詳細設計，並根據其資源要求進行器件選擇，然後使用protel工具進行電路板的製作。另外，本文還介紹了擴展板的調試方法，給出了邏輯模擬波形和調試結果。在此基礎上，本文闡述了協議晶元的配置方法，實現了1553b通訊擴展板間的通訊及中斷功能，達到了開發技術指標。
  5. The results of simulation prove that the improved algorithms are feasible for evolving the digital combinational logic circuits and improve the evolvable efficiency and convergence performance

    模擬實驗結果證明了改進演化演算法對于實現函數級數字組合邏輯電路的硬體演化是可行的，並且提高了演化演算法的演化效率和收斂性能。
  6. Evolvable algorithms are applied to functional digital combinational logic circuits with the structure of classicepglo chip of altera co. and the detailed analyses of typical examples are also given

    結合altera公司classicep610晶元的結構，研究了將演化演算法應用於函數級數字組合邏輯電路的硬體演化，並且對典型實例進行了詳細分析。
  7. The reactive power compensation is an important engineering in the power system. the active reactive power compensator designed in this text takes the instantaneous reactive power theory of three - phase as foundation, and is formed by the reactive current testing circuit, current tracking control circuit and the main circuit, and among them the current tracking control circuit is formed by instruction current arithmetic circuit, current polarity checkout circuit and current tracking control logic circuit three parts in the circuit form

    無功功率補償是電力系統中的一項重要工程，本文所設計的有源無功功率補償器是以三相瞬時無功功率理論為基礎的，它由無功電流檢測電路、電流跟蹤控制電路和主電路三大部分組成，其中電流跟蹤控制電路由指令電流運算電路、電流極性檢測電路和電流跟蹤控制邏輯電路三部分構成。
  8. Complex programmable logic device ( cpld ), usually used to develop asic, is widely used in digital system to accomplish complex combinational and sequential logic

    復雜的可編程邏輯器件（ cpld ）廣泛地用於數字系統中，常用作設計自己的專用集成電路，可實現復雜的組合邏輯和時序邏輯。
  9. Digital circuit includes two kinds - the assembly logic circuit and the sequential logical circuit, the characteristic of the assembly logic circuit is that the output signal is only the function which enters the signal and has nothing to do with the entering state at any other moment, it has no function of memory

    摘要數字電路分為組合邏輯電路和時序邏輯電路兩類，組合邏輯電路的特點是輸出信號只是該時的輸入信號的函數，與別時刻的輸入狀態無關，它是無記憶功能的。
  10. This thesis focuses on the ingress process module of ctu, which translates c - 5 dcp format to rainier 4gs3. the specification analysis, architecture and logic design, functional simulation testbench design, synthesis report and testing result are discussed in this thesis. the research work mainly includes : the specification analysis and design requirements of ctu logic ; the architecture and logical design of ingress process module, which includes receive control fsm, send control fsm and cell position adjustment logic ; the performance improvement of ingress process module to receive and transmit data cell at the full line speed

    本論文的主要研究工作包括：通信協議轉換邏輯的功能分析和設計需求；通信協議轉換邏輯上行方向的系統分析及體系結構設計，包括上行接收狀態機、發送狀態機、信元內位元組位置調整機制等的設計；通信協議轉換邏輯上行方向的線速設計，主要是上行接收的線速設計，要使用流水設計技術；提出了高速實現roundrobin調度策略的實現方法，並設計實現了桶式移位器和優先級編碼電路；應用bfm模擬模型設計了上行處理各模塊的模擬testbench ，完成了各級模塊的模塊模擬和系統集成模擬。
  11. Digital design ： binary system, boolean algebra, logic gates, simplification of boolean functions, combinational logic. analog design ： amplifiers, frequency response, feedback, operational amplifier

    數位設計：二進位制、布氏代數、邏輯閘、布氏函數的化簡、組合邏輯電路。類比設計：放大器、頻率響應、反饋系統、運算放大器。
  12. Design basis of combinational logic circuit

    組合邏輯電路設計基礎
  13. 1. a small and cheap 8 - bit microcontroller is used as control core. all components of the sensor, some of which are necessary for the multiple and intelligent functions, are selected ones with low cost and small package. by designing all auxiliary logic circuits in a complex programmable logic device ( cpld ), and integrating all analog circuits in an application specific ic ( asic ), the size of pcb board is greatly reduced, which make it possible that the pcb can be installed with the displacement detector together

    系統採用小型廉價8位微控制器控制，電路內配置了為實現多功能智能化所必需的硬體，並全部採用低價格、小體積器件，還將所有輔助邏輯電路設計在一片復雜可編程邏輯器件cpld內，所有模擬電路集成於一片專用集成電路asic內，大大縮小了電路板尺寸，再與傳感元件組裝在一起，從而使整個系統在保證智能化功能的前提下，具有體積小、成本低、一體化和抗干擾能力強的特點。
  14. Then studis on new models and new approaches based on boolean process in delay automation are made. analytical delay model is improved with the new concept of sensitization, based on which delay matrix is proposed to describe the delay of circuit modules. then introducing hierarchical delay analysis methods into delay matrix analysis, a novel exact hierarchical delay ananlysis method is presented

    在組合邏輯電路精確定時方面，本文用波形多項式偏導定義的敏化概念改進了解析延時模型，在此基礎上建立了基於敏化的延時矩陣以描述電路模塊的延時，隨后將層次化延時分析方法引入基於延時矩陣的延時分析中，形成一種新的精確的通用電路層次化延時分析方法。
  15. Digital combined logic circuit modeling and simulation based on matlab

    的數字組合邏輯電路建模與模擬
  16. Circuit design is the basis of design of demultiplexer. speed, power and chip area are the main factors that should be considered in circuit design. every circuit structure has its merits and drawbacks, e. g. cmos logic family has a slower speed, but lower power, smaller area, scfl ( source couple fet logic ) family has a higher speed, but higher power, larger area. we should choose a proper circuit structure or their mixed structure for certain design to get a good tradeoff among the three factors. flip - flop is the fundamental element of demultiplexer, setup time and hold up time are key factors, which influence the speed of circuit, thus the design aim is how to reduce them. in this thesis we place emphasis on the design of scfl latches

    速度、功耗、面積是電路設計要考慮的主要因素，不同的電路形式具有不同的優缺點，如cmos互補邏輯電路功耗低，面積小，速度相對較慢； scfl （源極耦合fet邏輯）電路速度高，功耗和面積較大。所以要針對具體設計需要選用適當的電路形式或其組合結構，以滿足設計要求。觸發器是分接器的基本組成單元，建立時間和保持時間是影響電路速度的關鍵，所以減小建立時間和保持時間是觸發器設計的主要目標，本文著重介紹了scfl鎖存器的設計和優化方法。
  17. Combinational logic circuit

    組合邏輯電路
  18. Analysis of competition and adventure in assembled - logic circuits using pspice simulation

    分析組合邏輯電路中的競爭冒險
  19. The analysis and designation on the assembly logic circuit is one of the important content of digital circuit

    組合邏輯電路的分析設計是數字電路重點內容之一。
  20. In this solution, the embedded soft cpu ip core is used as the kernel digital module with its periphery controllers based on residual les. in addition, analog channel circuit is added to form an integrated dso system. this dissertation focuses on framework construction, gui design, memory management, message fifo management, other hardware drivers and describes design and implementation of software simulation system written in advanced languages

    在這種方案中，使用了在fpga中嵌入cpu軟核作為控制核心，並用fpga晶元中剩餘的其他可編程邏輯資源構成該嵌入式系統的外圍器件，形成數字示波表的數字核心模塊，並配以模擬通道部分電路，組成了一個完整的數字示波表。
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