鐘行列式 的英文怎麼說
中文拼音 [zhōnghánglièshì]
鐘行列式
英文
principal minor- 鐘 : Ⅰ名詞1 (用銅或鐵製成的響器) bell 2 (計時器) clock 3 (指鐘點、時間) time 4 (沒有把兒的杯子...
- 行 : 行Ⅰ名詞1 (行列) line; row 2 (排行) seniority among brothers and sisters:你行幾? 我行三。where...
- 列 : Ⅰ動1 (排列) arrange; form a line; line up 2 (安排到某類事物之中) list; enter in a list Ⅱ名詞1...
- 式 : 名詞1 (樣式) type; style 2 (格式) pattern; form 3 (儀式; 典禮) ceremony; ritual 4 (自然科...
- 行列 : ranks
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The serializer and deserializer moduls in the ftlvds chip are designed by the way of standard cell design approach. the paper emphatically discusses the tradeoff and the implementation of several clock synchronization modes and circuit structures, and makes a lot of verilog simulation and verification on the circuits designed
串並模塊串列化器和解串列器採用標準單元的方法設計,論文討論了對幾種時鐘同步模式以及串並轉換電路結構的權衡和實現,並對所設計的電路結構進行了verilog模擬驗證。According to the reserved scanning address sequence, channel range and trigger mode, it can sample data. the module can change sample time and sample length. the sample data can be disposed by the cpu on board and then be stored in 64k ram
本模塊可根據預先設置的掃描地址序列、通道量程和觸發方式進行數據採集,采樣時鐘和采樣長度可以改變,測得數據經過板上cpu的實時處理后在64k的存儲器中緩存。An idea is brought forth to design the total structure of the usb interface ip, the main control logic, the mcu interface ( the function is the same as the pdiusbd12 chip of the philips semiconductor ) and a dpll which is used to synchronize data and separate the clock. this paper also introduces packet recognition, transaction sequencing, sop, eop, reset, resume signal detection / generation, nrzi data encoding / decoding and bit - stuffing, crc generation and checking ( token and data ), packet id ( pid ) generation and checking / decoding,
提出設計了usb介面電路的整體構架,設計了usb的主要控制邏輯和與mcu的互連的介面(此介面與飛利普的usb介面晶元pdiusbd12兼容) ,也設計了一個數字鎖相環( dpll )來同步數據和分離時鐘,並對同步模式的識別、并行/串列轉換、位填充/解除填充、 crc校驗/產生、 pid校驗/產生、地址識別和握手評估/產生做了具體的分析。
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