鐘表計時器 的英文怎麼說

中文拼音 [zhōngbiǎojìshíqì]
鐘表計時器 英文
clockwork timer
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 表 : Ⅰ名詞1 （外面;外表） outside; surface; external 2 （中表親戚） the relationship between the child...
  • 計 : Ⅰ動詞1 （計算） count; compute; calculate; number 2 （設想; 打算） plan; plot Ⅱ名詞1 （測量或計算...
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 鐘表 : clocks and watches; timepiece; horologe clock and watches
  • 計時器 : calculagraph; time meter; chronoscope; timer; time market; time totalizer; elapsed timer; running...
  • 計時 : reckon by time; timing; chronography
  1. Precious metals and their alloys and goods in precious metals or coated therewith, not included in other classes ; jewellery, precious stones ; chorological and chronometric instruments

    不屬別類的貴重金屬及其合金，以及不屬別類的貴重金屬製品或鍍有貴重金屬的物品珠寶，寶石鐘表和計時儀器。
  2. Class14 ： precious metals and their alloys and goods in precious metals or coated therewith, not included in other classes ; jewellery, precious stones ; horological and chronometric instruments

    類別14 ：不屬別類的貴重金屬及其合金，以及不屬別類的貴重金屬製品或鍍有貴重金屬的物品；珠寶，寶石；鐘表和計時儀器。
  3. Class 14 precious metals and their alloys and goods in precious metals or coated therewith, not included inother classes ; jewellery, precious stones ; horological and chronometric instruments

    商標注冊類別14不屬別類的貴重金屬及其合金，以及不屬別類的貴重金屬製品或鍍有貴重金屬的物品；珠寶，寶石；鐘表和計時儀器。
  4. Clock and form know together as. clock and watches all calculate with designation horary of precise instrument

    鐘和表的統稱。鐘和表都是計量和指示時間的精密儀器。
  5. Thirdly, the paper discusses the driver of the peripheral equipment, how to port the uc / os - n and uclinux, h. 323 protocol and the application of the system in the digital speech classroom. also some software and hardware measure are adopted to enhance the system stability. at last, the shortcoming and the something to be improved are given. dsp can be used to realize real - time speech coding algorithm, and after porting ( ac / os - n, arm can manage the keyboard, the lcd and the ethernet peripheral etc. then the embedded network system with specific purpose can be used in others fields, such as pda, set of top, web tv, ect

    在實際設計實現中，為提高系統軟、硬體整體穩定性和可靠性，使用了以下幾種方法： （ 1 ）低電壓復位、抗電源抖動能力、增加時鐘監測電路、抗電磁干擾能力、散熱等技術； （ 2 ）多層pcb設計，線路板結構緊湊，電源部分採用數字5v 、 3 . 3v 、 3v 、 1 . 8v和模擬5v多電源供電； （ 3 ）選用表面貼和bga封裝的器件； （ 4 ）按照軟體工程的要求進行系統分析，規劃系統框圖、流程分析、模塊劃分，減小了不同模塊的相關性，從而最大限度避免了錯誤的發生。
  6. The key to the fft algorithm is the design of butterfly computation and that of the address logic. the whole schema is designed in the top - down design flow and described in the vhsic hardware description language ( vhdl ), basing on these, we do our research on reconfigurable technology. the result indicates that the data processing ability of reconfigurable system improved greatly

    結果表明，可重構系統在數據處理能力方面比以往的系統有了很大的提高，本設計實現的fft重構處理器可工作於60mhz下，完成一個16點fft需要132個主時鐘周期，完成32點fft需要324個主時鐘周期，而且具有一定可重構性，可以方便地將其運算點數進行擴展，或將其他的圖像處理演算法在實時處理系統中實現。
  7. Produce software timer and stopwatch functions, but can also set a limit on the number of alarm clocks. the bacteria can be achieved through the use of multiple users set up, for example the user can be de

    此款軟體具有計時器和跑表功能，而且可以設定不限數目的鬧鐘，用戶通過使用可以實現多重鬧鈴的設置，比如用戶可以自定義在指定的某年某日某時，可以通過播放聲音閃動指示燈和使用震動來提示，而且附帶倒計時軟體和多功能的跑表，可以使用
  8. With our " caliber iv " we have created a chronographic movement which on the one hand lets appear the watch in a modest and noble character from the outside, but on the other hand offers to every watch enthusiast a great delight on technical raffinesse

    機芯帶有謙遜而不失高貴的個性，並讓鐘表熱衷者深深體會到它的精緻講究。他的特點是，控制輪被設計得使計時器顯示和分鐘計顯示看上去都來自於表中心。
  9. In the designed hardware, at89c51 single chip computer and many kinds of new type circuit chip ( including : special power measuring chip - cs5460a, ds1302 calendar / clock chip, sms0601 lcd, x5045 serial memory ) are used for design. the hardware circuit is simplified, the meter ' s anti - interference ability is enhanced and the precision of measurement is also advanced

    設計中以at89c51單片機為核心，採用多種新型集成電路晶元（包括電能計量專用晶元cs5460a 、 ds1302日歷時鐘晶元、 sms0601液晶顯示器、 x5045串列存儲器）進行介面設計，簡化了硬體電路，提高了電能表的抗干擾能力和測量精度。
  10. Using an 8 - depth async fifo solves the synchronization and exchange of data be - tween different clock domains. the data transaction protocol comes from the most basic work way of uart. when the master clock is 16. 7mhz, the pcm side and adpcm side clocks both are 2. 38mhz, the results of simulation show that the latency from the start - bit of pcm data inputting uart receiver to the stop - bit of adpcm data outputted uart transmitter is 14. 3 us and the latency from the start - bit of adpcm data inputting uart receiver to the stop - bit of pcm data outputted uart transmitter is 14. 7 us

    在主時鐘為16 . 7mhz ， pcm數據端與adpcm數據端時鐘均為2 . 38mhz時，模擬結果表明從pcm的起始位輸入uart接收器到adpcm終止位輸出uart發送器的最大延遲為14 . 3 s ，從adpcm的起始位輸入uart的接收器到pcm終止位輸出uart發送器的最大延遲為14 . 7 s ，設計時盡可能的使編碼與解碼的時間相差不多，從結果看出基本達到這個要求。
  11. Focusing on a 64 - bit high - performance general purpose microprocessor with fully independent intellectual property, the thesis investigates a 128 - word 65 - bit general register file with 12 - read and 8 - write ports which is a representational one for its large - scale and multi - port characteristics in that microprocessor, and realizes its full custom design with high speed in read and write access. from the layout simulation result, under the 0. 18um process, the upper limit working frequency for the register file is 900mhz

    本文面向一款具有完全自主知識產權的64位高性能通用處理器，對其中具有代表性的128字65位12讀埠和8寫埠的通用寄存器文件進行研究，實現了它的高速讀寫全定製設計，版圖模擬結果表明，在0 . 18um工藝下，設計可以工作的時鐘頻率上限為900mhz 。
  12. The speed of a computer is usually expressed in cycles per second. typical machines operate at 100 to 200 megahertz or 100 million to 200 million cycles per second

    計算機的速度通常用每秒（執行）的（時鐘）周期來表示。典型的機器運轉在100到200兆赫或者說每秒100到200兆周期。
  13. The report processing timer clock begins when the report is selected and ends when the report opens

    報表處理計時器時鐘在您選擇報表時開始運行，而在報表打開時結束運行。
  14. The third row of the table represents synchronous parallel loading of the register and states that if s1 and s0 are both high, then, without regard to the serial input, the data entered at a is at output qa, data entered at b is at qb, and so forth, following a low - to - high clock transition

    表2中第三行表示計數器的同步平行的加載，和表明如果s1和s0為高電平，那麼它就不是連續輸入，在時鐘由低向高跳變后，在a端的數據輸入則在qa端輸出，在b端的數據輸入將在qb端輸出，等等。
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