閂鎖 的英文怎麼說

中文拼音 [shuānsuǒ]
閂鎖 英文
breech lock; latch閂鎖電路 latch circuit; 閂鎖機 gunlock; 閂鎖繼電器 [電學] latching relay; latch-in relay; locking relay; 閂鎖全加器 latching full adder; 閂鎖狀態 latch mode
  • 閂 : Ⅰ名詞（門閂） bolt; latch Ⅱ動詞（用閂插上） fasten with a bolt or latch
  • 鎖 : Ⅰ名詞1 （安在開合處使人不能隨便打開的器具） lock 2 （姓氏） a surname Ⅱ動詞1 （上鎖） lock up 2 ...
  1. Two other effects are transient phenomenon called single event upset ( seu ) and single event latchup ( sel ). in this paper, some means to harden the devices against these phenomena are used. guard banding around nmos and pmos transistors greatly reduces the susceptibility of cmos circuits to lachup

    在本文設計中，採用雙環保護結構，大大的降低了cmos集成電路對單粒子閂鎖效應的敏感性；對nmos管採用環型柵結構代替傳統的雙邊器件結構，消除了輻射感生邊緣寄生晶體管漏電效應；採用附加晶體管的冗餘鎖存結構，減輕了單粒子翻轉效應的影響。
  2. A novel latched comparator with low kickback noise

    噪聲的閂鎖型比較器
  3. Bolt action repeating shotgun

    閂鎖式連發鳥槍
  4. Research on cmos latchup

    電路中的閂鎖效應研究
  5. A latch is primarily used to synchronize database pages

    閂鎖主要用於同步數據庫頁。
  6. Each latch is associated with a single allocation unit

    每個閂鎖與單個分配單元關聯。
  7. Maximum time a memory object has waited on this latch

    內存對象已等待此閂鎖的最大時間。
  8. Allocation page latching protocol is improved

    分配頁閂鎖協議得到改善。
  9. This counter is incremented at the start of a latch wait

    此計數器在閂鎖等待啟動時遞增。
  10. Number of waits on latches in this class

    此類中的閂鎖等待的個數。
  11. This reduces the number of up update latches that are used

    從而減少使用的up （更新）閂鎖數。
  12. This latch class covers all possible uses of page latches

    此閂鎖類覆蓋所有可能的頁閂鎖使用。
  13. Total wait time, in milliseconds, on latches in this class

    此類中閂鎖的總計等待時間（毫秒） 。
  14. 4 session id of the blocking latch owner could not be determined due to internal latch state transitions

    - 4 =由於內部閂鎖狀態轉換而無法確定阻塞閂鎖所有者的會話id 。
  15. 4 session id of the blocking latch owner could not be determined at this time because of internal latch state transitions

    - 4 =由於內部閂鎖狀態轉換，此時無法確定阻塞閂鎖所有者的會話id 。
  16. Lock up relay

    閂鎖繼電器
  17. Unlike locks, a latch is released immediately after the operation, even in write operations

    與鎖不同，在操作之後，甚至在寫入操作中，會立即釋放閂鎖。
  18. The n / n + and p / p + epitaxial structures, which become popular with the development of coms technology, because they can avoid the latch - up and a softerror of ulsi while they combined with the intrinsic gettering ( ig ) technique

    Coms工藝中普遍採用n / n ~ + 、 p / p ~ +的外延結構，這種以重摻雜矽片為襯底的外延結構與內吸雜工藝相結合，是解決集成電路中的閂鎖效應和粒子引起的軟失效的有效途徑。
  19. Soi hvic ( silicon on insulator high voltage integrated circuit ) is the mainstream and trend of the power integrated circuit ( pic ) due to the improved no latch - up, reduced leakage current, perfect irradiation hardness, and improved insulation

    Soi （ silicononinsulator ）高壓集成電路具有無閂鎖、漏電流小、抗輻射、隔離性能好等優點，已成為功率集成電路（ powerintegratedcircuit ）的重要發展方向。
  20. This paper also presented the structure of soi bjmosfet and discussed and analyzed the advantages of this device by comparing with the bulk bjmosfet. its advantages are as fellow : no latch - up effect, better capability of resisting invalidation, much smaller parasitic capacitance, weaker hot - carrier effect and short - channel effects, and simpler technics, and so on

    通過與體硅bjmosfet比較，討論和分析了soibjmosfet的優點：無閂鎖效應、抗軟失效能力強、寄生電容大大降低、熱載流子效應減弱、減弱了短溝道效應、工藝簡單等。
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