陣列邏輯 的英文怎麼說

中文拼音 [zhènlièluó]
陣列邏輯 英文
array logic
  • 陣 : Ⅰ名詞1 （作戰隊伍的行列或組合方式） battle array [formation]: 布陣 deploy the troops in battle fo...
  • 列 : Ⅰ動1 （排列） arrange; form a line; line up 2 （安排到某類事物之中） list; enter in a list Ⅱ名詞1...
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 陣列 : [統計學] array陣列處理機 array processor; 陣列印表機 array printer; 陣列雷達 [電學] array radar
  • 邏輯 : logic
  1. The hardware has two input channels of high - speed analog signal, with the signal amplitude of 0 - 5v, the conversion precision of 12bits, and the maximum sampling rate of 400ksps. this system includes 4 dsps ( adsp 2181 ), which can be arranged as a pipe line processing array. many algorithms can be realized in this system

    系統硬體有兩路模擬數據採集通道，模擬信號輸入范圍為0 ? 5v ，轉換精度為12位，最高采樣率400ksps ；系統包含4片dsp （ adsp2181 ）構成的流水線型的處理陣列，可用於實現各種演算法；系統的控制邏輯由fpga完成。
  2. In computers, a logic network in the form of an array of input leads andoutput leads with logic elements connected at some of their intersections

    在計算機中，由輸入線和輸出線陣列形成的一種邏輯網路，在它們的某些交叉點上用邏輯元件相連接。
  3. In computers, a logic network in the form of an array of input leads and output leads with logic elements connected at some of their intersections

    在計算機中，由輸入線和輸出線陣列形成的一種邏輯網路，在它們的某些交叉點上用邏輯元件相連接。
  4. In the third part, gives a new fft algorithm for realization ofdm modulation in fpga

    第三部分為在的現場可編程邏輯門陣列（ fpga ）上實現ofdm調制模塊。
  5. With the quickly development of field programmable gate array, fpga with more than million logic gates has been used

    隨著fpga （現場可編程門陣列）技術的快速發展，萬門以上乃至幾十萬門邏輯陣列的使用越來越普遍。
  6. The system uses the permanent magnet synchronous machine as the driver motor based on the idea of polygonal flux linkage locus and the permanent magnet brush - less motor is as the momentum balance motor by means of speed and current loop in order to track driver motor precisely and rapidly. the harmonious control of driver motor and balance motor is realized by making full use of the dsp hardware resource and complicated programmable logic device. the software design is composed of c and assembly language to realize motor control arithmetic of polygonal flux linkage locus

    衛星天線伺服控制系統以正弦波永磁同步電機作為驅動電機，採用多邊形磁鏈軌跡法（電壓空間矢量法）的控制策略；動量平衡電機採用永磁無刷直流電機，通過電流環、速度環達到快速、精確跟蹤驅動電機的目的，確保了衛星姿態恆定；設計方案中充分利用了dsp硬體資源和復雜邏輯陣列實現了驅動電機和平衡電機的協調控制，並通過c語言和匯編語言的混合編程實現了電機的多邊形磁鏈軌跡控制演算法。
  7. A set of two or more disks that may appear to the system as one large disk. a disk array can be either a software or a hardware device

    磁盤陣列：由一組兩個或者多個磁盤組成，就系統而言可以看作是一個大的邏輯磁盤。一個磁盤陣列不僅可以當一個軟體裝置，也可以當作一個硬體裝置。
  8. A magnetic processor constitutes an array of logic gates, each of them programmable individually by the software

    磁處理器由邏輯閘陣列所組成，其中每個閘都可以由軟體獨立編程。
  9. Cracking a data encryption and decryption system using multi - valued logic array

    對一種基於多值邏輯陣列變換的加解密系統的破解
  10. Pld refer to the programmable logic device. it is a kind of chip that can be written the design of integrated circuits into its logic arrays

    Pld是指可編程邏輯器件，是一種可將集成電路的設計用編程的方式寫入到其邏輯陣列結構中的一種晶元。
  11. Programmable logic array

    可編程序邏輯陣列
  12. Researched the methods to test configrable logic block ( clb ) and its sub - blocks. based on a “ divide and conquer ” methodology, the clb resources are divided into three basic blocks : logic units, carry logic module ( clm ) and lut ’ s ( look up tables ) ram - mode. the testing configurations are implemented based on a two - dimensional array structure for logic blocks

    主要基於「分治法」對clb及其子模塊進位邏輯（ clm ） 、查找表（ lut ）的ram工作模式等進行了測試劃分，分別實現了以「一維陣列」為基礎的測試配置和測試向量，以較少了測試編程次數完成了所有clb資源的測試。
  13. Gal : generic array logic

    通用陣列邏輯
  14. Thirdly, to design gateway control by gal apparatus

    應用通用邏輯陣列（ gal ）器件對通路控制進行設計。
  15. Cellular logic array

    細胞邏輯陣列
  16. Pla specification for harmonized system of quality assessment for electronic components - blank detail specification : programmable logic arrays

    電子元器件用質量評估協調體系規范.空白詳細規范:可編程序的邏輯陣列
  17. Pal : programmable array logic

    可編程陣列邏輯
  18. Cmos image sensor consists of image array logic registers, memory, timer pulse generator and converter

    Cmos圖像傳感器包括圖像陣列邏輯寄存器、存儲器、定時脈沖發生器和轉換器在內的全部系統。
  19. With the reconfigurable computing systems, the time of convolution processing is reduced to a fortieth of the computing on common pc versus without of it

    X86可重構計算系統由通用處理器和現場可編程陣列邏輯組成，該系統應當稱為混合系統。
  20. < 4 > validates the designs of des / rsa on the reconfigurable system test board, and discusses the further optimized approach of the designs. the research results will be contributive to the reconfigurable computing research in the field of encryption application of our nat ion

    本課題的設計與實現以航空微電子中心的可重構計算系統為硬體環境，此系統由通用處理器和現場可編程陣列邏輯組成，是混合系統，在當前一些應用領域如嵌入式微處理器系統等具有非常看好的應用前景。
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