高速數字通信 的英文怎麼說

中文拼音 [gāosùshǔzìtōngxìn]
高速數字通信 英文
high speed digital communication
  • 高 : Ⅰ形容詞1 （從下向上距離大; 離地面遠） tall; high 2 （在一般標準或平均程度之上; 等級在上的） above...
  • 速 : Ⅰ形容詞（迅速; 快） fast; rapid; quick; speedy Ⅱ名詞1 （速度） speed; velocity 2 （姓氏） a surna...
  • 數 : 數副詞（屢次） frequently; repeatedly
  • 字 : Ⅰ名詞1 （文字） character; word 2 （字音） pronunciation 3 （字體） form of a written or printed ...
  • 通 : 通量詞（用於動作）
  • 高速 : （高速度） high speed; high velocity （hv）; high rate; swift; fast; express; high-speed
  • 數字 : 1. （表示數目的文字; 表示數目的符號） figure; digit; numeral; character; numeric character 2. （數量） quantity; amount
  • 通信 : communication; communicate by letter; correspond
  1. Digital intermediate frequency system is one of the hotspots in radio communication and military research, it provided a superexcellent way for high - speed double direction digital communication

    數字中頻系統是當前軍事與移動通信領域的研究熱點之一，它為高速雙向無線數據通信提供了思路與方案[ 1 ] 。
  2. Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo

    本文首先對數字減影血管造影（ dsa ）成像系統的組成結構和數據流向進行了深入研究和分析，並對系統中的數據流向進行了完整的歸納和總結，給出了x線數字成像系統中的高速大容量數據通道的設計方案；在對sdram的控制方式做了深入探討后，給出了實現大容量多條sdram共同工作的解決方案，在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲；通過對pci總線介面的深入研究，優化後端狀態機設計和低層驅動程序開發，給出了完整的pci介面方案實現高速dma數據傳輸，完全可以滿足視頻傳輸要求；深入研究了基於大規模可編程器件的數字系統設計方法，針對通用fifo使能信號漂移、輸出數據難于建立和保持等設計難點，提出了利用fpga中的鎖相環提供多個時鐘相移的信號來提高系統穩定性的解決方案，從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。
  3. The services of electric power communication network have already expanded from telephone scheduling and transmitting data in low speed to digital user ' s service with high speed and great capacity, such as computer internet, wide area network and video transmission, etc. its structure has already developed from simple star topology, which is used to serve schedular center, to today ' s multicenter network to assure that the network can serve the requirement of increasing transmission of electric power information

    電力通信網的業務已從調度電話、低速率遠動數據傳送擴展到高速、數字化、大容量的用戶業務，例如計算機網際網路、廣域網、視頻傳送等。電力通信網的結構也已從單一服務于調度中心的簡單星形方式發展到今天多中心的網狀網路，以保證能為日益增長的電力信息傳輸需求服務。
  4. However, the paralleling communication can meet the requirements of high speed and fidelity in underwater signal transmissions. ofdm is a kind of novel paralleling transmission technology. the principle of ofdm is that the whole bandwidth can be divided into some subchannels, the high - speed serial signal stream is modulated by some orthogonal subcarriers

    正交頻分復用（ ofdm ）是近年來數字通信中流行的一種并行傳輸新技術，其核心思想是將整個可用頻帶分割成多個正交子通道，將待傳輸的高速串列碼流并行的調制在這些子通道載波上。
  5. In the following chapters, a 16 - channel experimental phased array ultrasonic testing system is thoroughly explained, including digital beam forming, low noise programmable amplification of received ultrasound signal, multi - channel hi - speed hi - precision data acquisition, hi - speed real - time processing of multi - channel ultrasound signal, and hi - speed data transfer based on pci bus. in addition, the frame of software system is built

    本文詳細闡述了作者所獨立研製的16通道相控陣超聲檢測實驗系統，包括數字化超聲發射/接收波束形成、超聲信號的低噪聲程式控制放大、多通道高速高精度數據採集、多通道超聲信號高速實時處理、基於pci總線的高速數據傳輸等全部電路模塊的結構及工作原理，並說明了所編寫的底層軟體系統的框架。
  6. Socket function mainly realizes setting up and initializing service unit socket, initializing service unit and service unit serial and so on. bind funcion primarily binds local address and port for the socket. listen function is to evaluate the max length of server ’ s listening queue. connect function and accept function set aside rate ahead, infrom user ’ s request of establishing virtual circuit to suna, cooperate with suna to establish the connection between client and server, return the result. we make use of three handshake with data protocol and virtual circuit mode, in this way, when we translate data, we can look up communication course according to virtual circuit number, at the same time, there aren ’ t source ip address and port, end ip address and port in the head of data package, the speed of translating data advances in a certain extent. send function and recv function is to send data collaborating with suna, and copy data from the receiving queue of socket to user ’ s buffer. close function cooperate

    Socket （ ）函數實現創建、初始化服務元套接字，初始化服務元及服務元序列等。 bind （ ）函數為套接字綁定本地地址和埠號。 connect （ ）和accept （ ）函數主要是根據用戶要求預留帶寬，將用戶的建立虛電路請求轉達給服務元網路體系，協作服務元網路體系採用捎帶數據的三次握手協議建立虛電路，並告訴用戶處理結果，一方面，捎帶數據的三次握手協議在一定程度上可提高數據傳輸速度;另一方面，採用虛電路方式，使得數據通信可直接根據虛電路號查找相應的通信進程，而且數據包的包頭中省去了源ip地址、埠號和目的ip地址、埠號，提高了數據傳輸速率。
  7. Secondly, basing on single channel if sr receiver mathematic model, this thesis has designed if sr receiver subsystem and brought forward its design project and system circuit principle diagram, and explained the system working principle. furthermore, this thesis introduces the working principles and respective applications of wideband high - speed adc ad6640, ddc ad6620 and high - speed dsp tms320c6713 according with the if sr receiver subsystem high - speed analog digital conversion department, digital down conversion department and high speed digital signal processing department. thirdly, the thesis emphatically demonstrates the software realization department of the if sr receiver subsystem, which including ad6620 ' s inner parameter software setup, tms320c6713 data transmission and processing and the quadrant demodulation algorithm program realization

    其次，基於單通道中頻軟體無線電接收機數學模型，本文設計了中頻（ if ， intermediatefrequency ）軟體無線電接收機子系統，給出了中頻軟體無線電接收機子系統的設計方案和系統電路原理圖，說明了系統工作原理，並分別對應系統中的高速模數轉換部分、數字下變頻部分、基帶數字碩士學位論文軟體無線電理論研究及中頻軟體無線電接收機子系統設計信號處理部分，介紹了高速adcad664o ，數字下變頻器（ ddc ， digitaldownconverter ） ad6620 ，高速數字信號處理器（ dsp ， digitalsignalproeessor ） tms320c6713的工作原理，以及它們在中頻軟體無線電接收機子系統中的應用。
  8. Research of adaptive spatio - temporal dfe with embedded dpll in high - speed underwater digital communication

    內嵌數字鎖相環的自適應空時聯合均衡器在水下高速數字通信中的應用研究
  9. In recently years, with the great progress made in the field of ic and digital communication, it is possible to integrate the whole high - speed digital communication system in a single chip

    近年來，集成電路和數字通信技術飛速發展，從而使高速數據廣播/傳輸系統的vlsi實現成為可能。
  10. Chapter 3 and chapter 4 introduce the most advanced measure systems. a series of solutions and design rules have been given according to simulations and real works

    第三章和第四章通過結合實際設計工作，介紹信號完整性問題的一些先進測量手段，並給出高速數字電路信號完整性問題的常用解決方案和設計過程。
  11. A design ot portable digital oscillograph based on dsp is presented. a integrated prototype is composed of high speed data processing module by which signal is digitalized, data processing unit whose core is dsp, general controller as which cpld is used and terminal facility - - lcd

    通過高速數據採集模塊將信號數字化，以高性能數字信號處理器tms320vc5402為核心構成數據處理單元，採用高密度的可編程邏輯器件epf6016a設計儀器的系統控制單元，使用液晶顯示器做為終端顯示設備，構成一個完整的示波表樣機。
  12. The fourth chapter introduces the designing and im - plementing about the hardware of high speed bert, and gives some actual design cir - cuits. the fifth chapter introduces the designing and implementing about the software of high speed bert, and gives the simulation results of some program blocks and top block. the testing parameters are given in the sixth chapter

    本文第二章介紹數字通信及復接技術的有關理論;第三章介紹高速誤碼率測試儀發端子系統的設計方案;第四章介紹高速誤碼率測試儀的硬體設計及實現過程，並給出了一些實際設計電路;第五章介紹高速誤碼率測試儀發送端軟體設計及實現過程，並給出了各程序模塊及頂層模塊的模擬結果;第六章給出了高速誤碼率測試儀發送端的測試參數。
  13. In the point of - information theory ; - the - baseband binary pulse amplitude modulated ( pam ) signal transmission, via turning the nonlinear receiver ' s parameters, is studied over an additive white gaussian noise ( awgn ) channel. it is demonstrated that the channel capacity of binary communication systems, for a given signal added noise, can be maximized by optimal designed receivers. this new form of sr is referred to as psr in a broad sense

    本文研究並設計了含有雙穩態隨機共振系統作為一個接收裝置的基帶數字通信系統，在加性高斯白噪聲通道中，通過研究這個非線性接收器的性能，發現了數字信號傳輸中存在的參數調節隨機共振現象?通道容量隨著系統響應速度的增加具有一個共振峰值，並對這種非線性現象發生的基本機理進行了解釋。
  14. The design combines the advantages of hardware " s high - speed and software ' s low resources : 1 ) mc145572 is chosen to access the net providing 128kbit / s, 2b + d full dual channels ; 2 ) because of b channel " s large amount of user data and its high demands of real - time performance, the gsc hardware channel of intel 80c152 used as cup of the system is used to wrap / unwrap b channel " s sdlc, ensuring the system real - time working

    第一，選用motorola的mc145572晶元來實現終端在u節點的n ? isdn的物理接入。提供2b + d通道的全雙工的數字通信，速率達128kbps 。第二， b通道承載數據量大，實時性要求高，採用intel80c152作為cpu ，利用其gsc硬體通道實現b通道數據的sdlc （同步數據鏈路）裝幀與解幀，以確保通信的實時性。
  15. Mpeg - 2 is an international standard about digital motion picture and audio signalizing for using in telecomunication, broadcasting, storage media and computer field established by iso / iec [ 1 ], [ 2 ]. hdtv ( high definition television ) technology integrates the most advanced image compression encoding technology and the digital communication technology, which is representative of the third generation television

    Mpeg - 2作為數字視頻壓縮技術和國際通用標準，在視聽工業、多媒體通信、數字視頻廣播以及未來的信息高速公路等領域有著廣闊的前景。高清晰度電視（ hdtv ）是當今世界上最先進的圖像壓縮編碼和數字通信技術的結合，是第三代電視的標志。
  16. Through using si analyse in the hardware design of a dtv set top box ( stb ), the main contribution of this paper is to give a series of solutions for si problems according to theoretically analyse and real works. advanced measuring systems have also been shown in the paper. with the help of this paper, the stb system of a world famous corporation has successfully get wide using of ddr sdram

    本文的主要工作是在針對消費類電子（ consumerelectronics ）領域中的數字電視接收機頂盒進行硬體設計的過程中，引入信號完整性分析的設計方法進行高速數字電路的設計，利用理論分析作為設計指導，通過測量、模擬和實際布板的結果進行驗證，得出一系列針對信號完整性問題的解決方案和設計流程，成功地解決了某世界著名企業的機頂盒系統中ddr存儲器工作頻率無法提高的問題，在新一代的機頂盒產品中廣泛使用ddr存儲器，在很大程度上提高了系統的性能，滿足了市場的需求。
  17. Adopting advanced sdh light cable transmission facilities, the group exchange net, ddn data telecommunications net, isdn wide band net and xinji information net. xinji has advanced financial system

    採用sdh先進的光纜傳輸設備，建成了分組交換網ddn數字數據通信網， isdn寬帶和高水平辛集信息港，形成了高速大容量互動式的現代信息網路。
  18. Vliw architecture integrates many executing units. the parallel working of these executing units greatly progressed the performance of dsp. this kind of dsp is more and more widely used in multi channel high - speed digital signal process

    Vliw體系結構的dsp是近幾年出現的一種高性能dsp ， vliw體系結構在一塊dsp中集成多個執行單元，多個執行單元并行操作，極大地提高了dsp的性能，越來越多地用於多通道高速數字信號處理。
  19. During the last century, the vhf ( very high frequency ) communication has been applied in the ship ' s transportation, as well as radar and arpa also could identify ships in the marine. but they could n ' t adapt to the needs of the modern navigation because of their limits. the rapid development of the digital communications technology, computer technology and net ware technology supports the needed technology of ais ( automatic identification system )

    上個世紀， vhf通信技術被廣泛地應用於船舶通信；雷達、 arpa具有識別船舶的功能，但是由於自身的局限性而無法適應現代航運安全的需求；隨著數字通信技術、計算機技術以及網路信息技術的飛速發展， ais的技術基礎已經搭建好，在航運界對助航設備的要求越來越高的情況下，船舶自動識別系統應運而生。
  20. This high speed digital test module is based on the vxi bus structure and specified on multi - channel and high speed aspects ; it is also capable of generating the stimulant signal and collecting the responded data ; meanwhile because the relationship between stimulation and response can be programmable, the module is highly intellective and it helps the testing system work more automatically ; what ' s more, with the good functions like real - time comparison, branch, single step, pause, trigger, it makes the testing more efficient as well

    本實驗室設計實現了高速數字測試模塊，該模塊是採用vxi總線結構的儀器，具備以下功能:多通道，高速度;同時具備產生激勵信號和採集響應數據的能力;能夠通過編程在激勵和響應之間建立起因果聯系，使整個測試過程體現出一定的智能性，大大提高測試系統的自動化程度;具有實時比較，實時跳轉，單步，暫停，觸發等功能，使測試過程更加快速和靈活。
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