高速緩沖內存 的英文怎麼說
中文拼音 [gāosùhuǎnchōngnèicún]
高速緩沖內存
英文
ram cache- 高 : Ⅰ形容詞1 (從下向上距離大; 離地面遠) tall; high 2 (在一般標準或平均程度之上; 等級在上的) above...
- 速 : Ⅰ形容詞(迅速; 快) fast; rapid; quick; speedy Ⅱ名詞1 (速度) speed; velocity 2 (姓氏) a surna...
- 緩 : Ⅰ形容詞1 (遲; 慢) slow; unhurried 2 (緩和; 不緊張) not tense; relaxed Ⅱ動詞1 (延緩; 推遲) d...
- 內 : 名詞1. (內部; 里頭; 里邊) inner; inside; within 2. (妻子或妻子的親屬) one's wife or her relatives 3. (姓氏) a surname
- 存 : 動詞1 (存在; 生存) exist; live; survive 2 (儲存; 保存) store; keep 3 (蓄積; 聚集) accumulat...
- 高速 : (高速度) high speed; high velocity (hv); high rate; swift; fast; express; high-speed
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Pipelining, superscalar organization and caches will continue to play major roles in the advancement of microprocessor technology, and if hopes are realized, parallel processing will join them
在微處理器技術的發展中,流水線操作、超標量體系結構和高速緩沖內存儲器仍將扮演著重要的角色。如果可能,平行處理方法也會加人。To use an intermediate storage ( magnetic disc ) when making a data transfer between highspeed storage ( usually main storage ) and a device that operates at a lower speed
當高速存儲器(通常是內存)和低速運行的(外部)設備之間進行數據傳送時,利用中間存儲器(磁盤)作緩沖(的技術或過程) 。It eliminates the need for agent blocks to have specific knowledge of ram array behind it. it takes care of protocols and latencies in an effort to simplify memory access by the agent blocks. agent blocks " see " a single linear frame buffer, all paging and bank swapping is handled by the and is transparent to the agent blocks
在嵌入式系統晶元中高速存儲器介面控制電路是系統必不可少的重要組成部分,由於有了存儲器介面的存在,使得系統內部客戶模塊不必專門了解存儲器本身的復雜特性,而只需關心傳輸協議和一些定義的遲滯參數,在客戶看來存儲器僅僅是一個線性的幀緩沖器,所有的換頁、區段切換都交由介面電路來處理,從而大大簡化了客戶對存儲器操作的復雜度。Secondly, he establishes a rule table of vehicles " behaviors based on analyzing them. the table can simplify the model of vehicle ' s following and lane changing so that it will shorten the time of simulation. and thirdly, by using the cache technology of level - two time cell, the author solves the conflict, which arises from the limited memory and the masses of cache that is needed to get the better precision in simulation
本文在系統設計中,用匝道控制和主線控制相結合的方法,進行高速公路全線交通的綜合控制,優化控制效果;根據車輛行為分析,建立了車輛行為規則表,將車輛跟馳模型和換道模型簡化為車輛行為表,減少了模擬時間;採用二級時間片的緩沖技術,解決了模擬過程為達到較高模擬精度所需的大量緩存與有限內存空間的矛盾。However, with many burst traffic simultaneously arriving at a node, the queue length may become larger and buffer overflow in a moment, or high - speed link is emerged into slower one, there will be in congestion
然而,當多個突發業務同時到達一個節點時,緩存隊列長度迅速增加,在極短的時間內出現緩沖溢出,或高速鏈路接入慢速網路中引起輸入鏈路速率大於輸出鏈路速率,則導致網路擁塞。Traditional methods such as emulation can do little about it, it has to introduce some new arts. on the path of modern computer and cpu designing, the registers, level 1 cache, level 2 cache on the chip and level 3 cache on the mainboard, plus ram, hard disk or floppy disk or flash disk, make up of the modern multi - hiberarchy storage architecture
現代計算機和cpu設計中, cpu片內的寄存器、一級高速緩存( level1cache )和二級高速緩存( level2cache ) ,主板上的三級高速緩沖,再加上主存,外存(硬盤、軟盤、電子盤等) ,構成了現代計算機的多級存儲體系結構。It contains two a / d channels, every channel has a 4kx 16bit buffer. it has three flexible trigger modes : inner trig, outer trig and software trig. vvp platform can support up to 4 plug - in boards ( 8 channel a / d ) to work together
該模塊作為一塊vvp儀器平臺上的插板,採用20msps的16位a d轉換器,一塊插板上設計了2個高速a d轉換通道,每個通道有4k 16位的緩沖存儲器,可以內部觸發、外部觸發和軟體觸發。In practice, the file system calls the kernel cache manager, which fulfills requests from an in - memory cache if possible and makes recursive calls to the file system driver to fill cache buffers
實際上,文件系統調用內核高速緩沖存儲器管理器,這個管理器執行來自於一個內存中的高速緩沖存儲器的請求,如果可能的話,並且遞歸調用文件系統驅動來填充高速緩沖存儲器。Since a cache memory system can reduce the need for main memory access, it greatly reduces the potential memory access contention in shared memory multiprocessor systems
可以把cache看成是主存與cpu之間的緩沖適配器,藉助于cache ,可以高效地完成dram內存和cpu之間的速度匹配。分享友人