architecture instruction set 中文意思是什麼

architecture instruction set 解釋
指令集結構
  • architecture : n. 1. 建築學。2. 建築（樣式、風格）；建築物。3. 構造，結構；【自動化】（電子計算機的）架構，體系結構。
  • instruction : n. 1. 教育，教導。2. 教訓，教誨。3. 〈 pl. 〉 指令，訓令，指示，細目。
  • set : SET ＝safe electronic transaction 安全電子交易〈指用信用卡通過因特網支付款項的商業交易〉。n 【埃...
  1. On the base of analyzing the sparc instruction set, this paper researches the pipeline technology and the resolution of correlation problems, and these problems were resolved by using the harvard architecture, internal forwarding and delay branch technology

    本文在分析sparc指令系統的基礎上，研究了流水技術及其相關問題的解決方法，並通過在硬體上使用哈佛結構、提前寫寄存器的操作時間以及內部前推和延遲轉移等技術較好的解決了結構相關、數據相關和轉移相關的問題。
  2. Other differences lie in the instruction set, internal architecture, and control signals.

    其他差別是在指令系統，內部結構和控制信號方面。
  3. The armp, which is controlled by a pipeline mechanism, has excellent real time performance and supports precise interrupt. the armp is compatible to powerpc 603e instruction set architecture ( isa ), and will be implemented by 0. 25 m cmos technique

    該處理器具有自主版權，採用自主設計的流水線結構進行控制，具有優良的實時性和精確中斷的特點，在指令集上與powerpc603e指令集完全兼容。
  4. Specifies the target architecture instruction set

    指定目標體系架構的指令集。
  5. After analyzing and comparing different partition rules, md32 pipeline architecture is finally defined, which meets the required instruction function, frequency and timing spec of md32. a complete set of creative design method for risc / dsp md32 micro - architecture is presented, such as parallel design, internal pipeline, central control, etc. thanks to the adoption of these design methodology, control path and data path are separated, circuit delay is reduced, and complex instruction operations are balanced among multiple pipeline stages

    它們將若干復雜指令操作均勻分配在幾個流水節拍內完成，實現了任意窗口尋址等復雜指令操作，將整個處理器的數據通路與控制通路分離，減小了電路時延，從而滿足了risc dsp不同指令功能和系統時鐘頻率的要求，構成了統一的、緊密聯系的、協調的md32系統結構。
  6. This architecture became known as risc reduced instruction set computer

    這種體系結構稱為risc （精簡指令集計算機） 。
  7. Superscalar risc microprocessor is the further development of reduced instruction set computer, it improve the instruction - level - parallism by means of adding parallel pipelining function units and dynamic on - chip scheduling. this thesis anslysises the architecture and the diversified techniques of superscalar computer

    超標量risc微處理器是精簡指令結構（ risc ）的進一步發展，它通過增加并行流水執行單元並結合片上硬體動態調度來提高指令并行度。
  8. It aims at reducing the number of execution cycles of instructions, and has experienced from the period of single issue architecture to the period of multiple issue architecture. in the past twenty years, risc has become more and more mature abroad. it makes great sense to develop our own risc and it is a effective way to develop our own risc with the instruction set which is compatible with those of risc which has been widely used

    80年代初出現的risc技術是計算機體系結構的重大變革，它以減少指令執行的平均周期數為結構設計的主要目標，經歷了從單發射結構到多發射結構的演變過程，解決了深度流水技術、相關技術、轉移預測技術、編譯優化技術等一系列技術難點，在20多年的時間里， risc技術的發展已日趨成熟與完善微處理器在軍事和民用領域都有著廣泛的應用，研製具有我國自主獨立版權的微處理器在當今具有重大意義。
  9. A bus shared heterogeneous architecture consisting of one or more instruction set processor cores, one or more dedicated hardware ip cores and one or more on - chip memories usually provides a good solution

    基於總線互連的由一個或多個指令集處理器核、一個或多個專用硬體ip核、一片或多片片上存儲器構成的異質體系結構成為媒體系統晶元的合理選擇。
  10. This paper presents the yh ts - 1 instruction architecture, which based on the vector expansion of arm v4 instruction architecture. it supports vector processing and scalar processing in the same instruction set

    本文提出了基於armv4指令集體系結構擴展的銀河ts - 1指令集體系結構，在同一個指令集內同時支持標量機制和向量機制。
  11. By referring to the definition of computer architecture, network architecture and software architecture, it defines the supply chain information architecture and setup one of the architecture it uses the above set - up supply chain information system architecture as the instruction, combines the current status of china motor industry supply chain, conducted a detail research of the architecture, setup a total architecture, model and detail analyze each sub - system ' s function and setup the function model

    參照計算機體系結構、網路體系結構以及軟體體系結構的定義，提出了供應鏈物流信息系統體系結構的定義，建立了供應鏈物流信息系統的一種體系結構。以建立的供應鏈物流信息系統體系結構為指導，結合我國汽車製造業供應鏈物流的實際情況，對汽車製造業供應鏈物流信息系統的系統構成進行了詳細研究，建立了其總體結構及功能模型，詳細分析了各分系統的功能構成並建立了功能模型。
  12. Isa instruction set architecture

    工業設置架構
  13. The features of instruction set architecture and application programs are the key factors to microprocessor architecture

    指令系統和應用程序的特點是決定微處理器體系結構的關鍵因素。
  14. By the analysis of jvm instruction set architecture and the measurement of typical java application programs, the crucial problems to be resolved are ascertained

    本文首先通過對java虛擬機指令系統的分析和對java典型應用程序的測試，提煉出java虛擬機指令的執行特點，明確了java晶元系統中需要解決的關鍵問題。
  15. Traditional reduced instruction set computer ( risc ) and digital signal processor ( dsp ) have different application areas due to their different instruction set architecture ( isa ) and micro - architecture

    傳統的精簡指令集處理器（ risc ）和數字信號處理器（ dsp ）各自具有不同的指令集結構和微結構特點，適合於不同的應用領域。
  16. We propose two implementations of momr : one employs only hardware changes while the other uses instruction set architecture support. we show that momr execution leverages available resources in typical multi - issue processors with minimal additional cost

    我們提出了momr的兩種實現：一是利用硬體的改變而是使用instruction set architecture指令集體系結構，簡稱isa的支持。
  17. High performance retargetable instruction - set architecture simulation technique

    高性能可重構指令集架構模擬技術
  18. The powerpc architecture is organized into three instruction - set levels called " books. " book i is the base set of user instructions and registers that should be common to all powerpc implementations

    Powerpc體系結構的指令集分為三級，稱為「 books 」 。 book i是基本的寄存器和指令集，所有的powerpc實現都通用。
  19. Although gpu has a very high computing speed, algorithms implemented in cpu cannot be put to execute in gpu directly because of the discrepancy in instruction execution manner of the two. gpu ' s architecture is a high parallel simd instruction set system. to reimplement algorithms insufficient to run on cpu with programmable graphics hardware, it has to reconsider the data structures and procedures to implement them to make full use of the

    雖然gpu具有非常高的計算速度，但並不能將以前在cpu中實現的演算法直接放到gpu中來執行，這是因為gpu的指令執行方式和cpu不一樣， gpu的體系結構是一種高度并行的單指令多數據（ simd ）指令執行體系，所以要在可編程圖形硬體上實現在cpu中效率不高的演算法，就需要重新制定演算法實現的數據結構和步驟，以充分利用gpu并行處理體系結構帶來的性能優勢。
  20. A novel 32 bit embedded fix - point superscalar risc core is developed. then we analysis the power dissipation of risc core from view of instruction - set - architecture, datapath, supply voltage and dynamic power optimization

    並從系統層次對risc處理器進行功耗分析，分別從改進指令體系結構、處理器數據通路、降低系統工作電壓和動態降低功耗四個方面進行低功耗研究。
分享友人
分享到 Line

分享到臉書