architecture of memory 中文意思是什麼

architecture of memory 解釋
記憶中的建築
  • architecture : n. 1. 建築學。2. 建築（樣式、風格）；建築物。3. 構造，結構；【自動化】（電子計算機的）架構，體系結構。
  • of : OF ＝Old French 古法語。
  • memory : n. 1. 記憶；記憶力；【自動化】存儲器；信息存儲方式；存儲量。2. 回憶。3. 紀念。4. 死後的名聲，遺芳。5. 追想得起的年限[范圍]。
  1. Applying two perpendicular polarized light states and a no - light state to express information, this new theoretical system covers : a ) whole architecture constructed from light processing, light transmission, electric control and photoelectric input and output ; b ) various computing units mainly consist of liquid crystal element and polarimeter ; c ) light bus mainly consists of interlinkage optic valves ; d ) ternary memory formed from semiconductor memory ; e ) register formed from optic fiber ring ; and i ) huge - numeral management based on the new concept of calculating path and calculating channel

    這個理論包括：光處理、光傳送、電控制、綜合輸入輸出的總體結構；以液晶元件和偏振器為主的各類運算器結構；以互連光閥為主的光空間總線；以半導體存儲器為主的三值數據存儲器結構；以光纖環為主的寄存器結構；以算位、算道新概念為基礎的巨位數管理方案等。
  2. This method can save the space of memory and reduce the computation time. because only the parameters of scattering centers are stored and genetic algorithm is used to search for aspect angle, the method is very suitable for the employment in real - time and restrictive environment. in chapter 3, the architecture of mmw seeker is studied

    該方法以目標多散射中心理論為基礎，只需要存貯目標的三維散射模型參數，需要的存貯量較少；與常規的全姿態角匹配識別方法比較，基於目標散射模型的匹配識別方法，由於利用了遺傳演算法的全局尋優能力，計算量較小。
  3. Risc processors generally feature fixed - length instructions, a load - store memory architecture, and a large number of general - purpose registers and / or register windows

    Risc處理器一般的特徵是固定長度的指令集，一個負載儲備存儲結構，和大量通用寄存器，及寄存器窗口。
  4. Many mcus use the harvard architecture, in which the program is kept in one section of memory usually the internal or external sram

    很多mcu使用harvard體系，程序保存在內存的一段中（通常是內部的或外部的sram ） 。
  5. With turning the scale of asic ( appl ication specified integrated circuits ) to s0c ( system on chip ), which conunon1y is composed of mcu, specified function ip cores, memory, periphery interface etc, the ip reuse techno1ogy is very important in s0c design flow, which can realize the constructions of different levels components. the approach of configurable system, method and design f1ow for udsm ( u1tra deep sub micron ) asic, logic system design using hdl 1anguage, coding style, static and dynamic verification strategy are a1so presented in chapter 2. in chapter 3 we study the vlsi - - dsp architecture design, dense computation and high speed high performance digital signal processing unit structure, which includes high speed mac components and distributed arithmetic unit

    在工程設計方法及結構化設計和高層次綜合的研究中，介紹了在深亞微米工藝條件使用的方法和asic設計流程，討論了高層次綜合的核心如何從描述推出電路構成的設計思路，針對不同目標的設計技巧討論了採用hdl語言進行邏輯系統設計的方法，給出了用vhdl語言進行代碼設計時的規范和風格，在面向soc的驗證策略討論了動態和靜態的驗證技術，提出了進行單獨模塊驗證、晶元的全功能驗證和系統軟硬體協同驗證的整體策略。
  6. Cluster system is one of the hot spots in the research area of high performance computer, while system area network ( san ) that used to connect nodes is considered to be the key point in the cluster system the aims of this paper are to study dedicated high performance san network based on distributed shared memory architecture, and set up cluster system with high price performance ratio the main work and originalities in this paper list as followings : 1

    群機系統是高性能計算機研究領域的熱點之一，而用於連接群機系統內部結點的系統域網路（ san ）是群機系統研究的關鍵。本文在分佈共享存儲器結構的基礎上研究高性能專用san網路，構建高性能/價格比的群機系統。本文的主要工作和創新點如下： 1
  7. Abstract : through plan and design of museum in memory of ren bi - shi, the authors study and explore the problems such as relation of building a nd site, the design of space around of building, how to inherit and expand tradi tional architecture in architectural language to some extent in this paper

    文摘:通過任弼時紀念館的規劃與設計，從理論和實踐兩個方面，對紀念館設計中建築與場所的關系、建築空間秩序的設計，以及建築語言表達中傳統建築的繼承與發展等問題進行了一定的研究與探索。
  8. It discusses the architecture of testbench in functional verification of dtv chip and detailed accounts realization of memory bist ( build in self test ) method

    本章介紹了各種主流驗證測試方法，著重敘述了dtv晶元中功能驗證的平臺結構設計和存儲器內建式自測試（ bist ）的具體實現。
  9. The dm642 uses a two - level cache - based architecture, level 1 cache is composed of a 16 - kbit l1p ( level 1 program cache ) and a 16 - kbit l1d ( level 1 data cache ), level 2 cache consists of 256 - kbit memory space that is shared between program and data space

    同時，研究了消除欠采樣噪聲演算法，並實現其處理功能。本文提出的系統設計方案，實現了高速、穩定、靈活的視頻採集處理播放平臺，可以高速而穩定的持久運行，達到了設計的要求。
  10. Based on the theory model of quantum computing and the quantum computing technique in existence, we have proposed the cooperating architecture of quantum computer. in this architecture, it uses the classic processor as its control unit, and use the quantum arithmetic logical unit and quantum memory unit as its co - process unit

    針對這種情況，通過對量子計算技術的深入研究，全面剖析現有量子計算系統，借鑒經典計算機中的研究成果，作者提出了協同量子計算機體系結構方案，在該方案中，使用經典計算機完成量子程序中的常規數據處理和程序邏輯控制，而將量子計算部件做為協處理器，只負責完成量子計算。
  11. Abstract with the foundation of real - time, fault tolerant, standard compatibility, a standard for embedded real - time os was suggested, which included embedded os architecture, supported hardware, schedule management, memory management, inter ? process communication, timer performance, network support, file system, driver development and debug and so on

    摘要以與實時系統開發過程密切相關的實時性、故障容錯和標準兼容性等關鍵特徵為基礎，提出一套對嵌入式實時操作系統性能衡量的標準，涵蓋體系結構、硬體支持、調度管理、內存管理、進程間通訊、定時性能、網路支持、文件系統、驅動編程以及開發調試等關鍵特證。
  12. With the foundation of real - time, fault tolerant, standard compatibility, a standard for embedded real - time os was suggested, which included embedded os architecture, supported hardware, schedule management, memory management, inter - process communication, timer performance, network support, file system, driver development and debug and so on

    摘要以與實時系統開發過程密切相關的實時性、故障容錯和標準兼容性等關鍵特徵為基礎，提出一套對嵌入式實時操作系統性能衡量的標準，涵蓋體系結構、硬體支持、調度管理、內存管理、進程間通訊、定時性能、網路支持、文件系統、驅動編程以及開發調試等關鍵特證。
  13. In the dissertation ， we discribe the implementation of large capability video data acquisition system based on pci bus of computer 。 the system is composed of data acquisiton card and corresponding software 。 the data acquisiton card include two acquisition channels ， 8 - bit digitization at rates up to 13. 5mhz 。 frist ， the architecture of the video data acqusition system is studied 。 then ， the function and implementation methode of each module are introduced in detail 。 the control module of the video data acqusition card is implemented by using of the isp technology of cpld and vhdl programming technology 。 the a / d converter used assembler to implement the initialazation programe 。 and the double buffer technology is used for large capability data acqusition. because a contiously large memory is difficult to apply in windows operating system 。 finally we use broland c + + to introduced the devleoping procedure of drivers 。

    在實際的研製過程中，利用cpld的在系統可編程（ isp ）技術和基於vhdl語言的可編程邏輯器件設計技術實現了視頻數據採集卡的控制模塊。在視頻的a / d轉換模塊，用匯編程序模擬i2c總線對初始化a / d轉換晶元。針對大容量數據採集，採用了雙緩沖技術解決wndows操作系統下難以申請到大容童連續內存的間題。
  14. In the paper, the system architecture of the edbms based on the ems memory is pinpointed. those pivotal techniques in the development of the system, including the physical memorizer management, query process, data synchronization and other technology are further discussed

    在這個思想的指導下，本文重點考慮了基於內存的嵌入式數據庫管理系統的體系結構，採用了有效的物理存儲管理機制、查詢處理和數據同步技術，並對關鍵部分的實現方式進行了詳細討論。
  15. The on - chip memory performance of embedded systems directly affects the system designers decision about how to allocate expensive silicon area. a novel memory architecture, flexible sequential and random access memory fsram, is investigated for embedded systems

    而我們開展的一項研究驗證了一種新型低功耗的片外存儲器結構的性能潛力，即靈活的順序與隨機存取存儲器lexible sequential and random access memory ，簡稱fsram 。
  16. In the first part, this paper discusses the key problems in designing architecture of each component, which include why we choose partitioned regiater files, use 2 - way connected data cache with write - back strategy and add scratch - pad sram to original momory system, and how to identify their parameters. following that, a memory configuration based on the discussion above is presented

    本文首先介紹了dpc各個存儲器的設計和實現，詳細討論了寄存器文件分體結構的選擇並提出了寄存器文件參數配置的四條規律，介紹了數據cache容量及策略的權衡與選擇，闡述了scratch - padsram與cache並存的優勢。
  17. Some resource - limited small devices cannot join jini network directly due to the inadequate processor power and small memory size. in order to implement the function of plug - and - play for such devices, the jini surrogate architecture technology can be used

    對于那些資源有限的小型設備，由於受處理器能力、內存大小的限制，沒有足夠的能力運行java虛擬機以加入jini網路者，這些設備要利用jini實現即插即用，必須採用jini代理體系結構技術。
  18. The book, written by ken arnold, provides a comprehensive overview of embedded microcontroller architecture, design, memory techniques, handling interrupts, and more

    書中所寫肯阿諾德，提供了全面的概述嵌入式微架構，設計，存儲技術，處理中斷等。
  19. Following the architecture description of rtps middleware, two critical implementation issues are carried out : the first, object - oriented multi - threaded architecture. to avoid negative effect brought by the block, and to improve the realtime responsive ability of the system, we decouple the event processing from its transportation ; the second, pooled memory allocationjn order to decrease the time - and - space overhead due to dynamic memory allocation, thus to improve the dynamic performance of the realtime publish - subscribe system and the predictability of runtime end - to - end qos, we adopt the pooled allocation to change many dynamic system calls into one static system call and several user interface calls in fixed time

    通過將事件的輸送與處理解耦以避免阻塞所帶來的影響、改善系統的實時響應能力，通過面向對象的多線程並發以支持異步事件的實時並發處理並獲得系統結構上的靈活性；其二，池式內存分配。通過內存池分配方式將客戶的大量動態系統調用轉化為一次靜態系統調用和數次固定時間的用戶介面調用以減少動態內存分配的時空開銷，從而改善實時發布-訂閱系統的動態性能與提高其運行時端對端服務質量的（ end - to - endqos ）可預測性。
  20. The article introduces the architecture of tms320c32 and the special addressing of dsp, completes the interface circuits between dsp and memory, pci bus, ad converter

    本文介紹了ti公司的tms320c32的體系結構和dsp特有的尋址方式。完成了dsp與存儲器、 pci總線以及ad轉換器等的介面電路的設計。
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