arithmetic and logic circuit 中文意思是什麼

arithmetic and logic circuit 解釋
算術與邏輯電路
  • arithmetic : n. 1. 算術，演算法；計算。2. 算術書。
  • and : n. 1. 附加條件。2. 〈常 pl. 〉附加細節。
  • logic : n. 1. 邏輯，理論學。2. 推理[方法]；邏輯性，條理性。3. 威力，壓力，強制（力）。
  • circuit : n 1 （某一范圍的）周邊一圈；巡迴，周遊；巡迴路線[區域]；迂路。2 巡迴審判（區）；巡迴律師會。3 【...
  1. This paper mainly aims at the characteristics of the hardware and software structure of the parallel computer on satellite, and has fulfilled researches of fault tolerant technique in three aspects of control theories and engineering : the first research of the system level fault - tolerant module is based on the system structure of the parallel computer on satellite, a kind of cold backup module and a kind of hot backup module for multiprocessor computer have been put forward. then the research of software fault tolerant technique which is based on the operate system named rtems has been carried, the mission level fault - tolerate arithmetic and the system level fault - tolerate mechanism and strategies based on the check point technique have been put forward, at the same time the self - repair technique of software which has used the technique of system re - inject has been studied. finally the technique of components level fault - tolerant based on fpga has been studied, a kind of two level fault - tolerant project which aims at the fault - tolerant module of the parallel computer on satellite has been put forward, and the augmentative of circuit that project design realization need is little, this project can avoid any breakdown of any part logic circuit of the fpga

    本課題主要針對星載并行計算機體系結構及軟體結構的特點，從如下三個方面進行了容錯控制理論研究和實踐工作:首先進行了基於星載多cpu并行計算機體系結構的系統級容錯模型研究，提出了一種多cpu冷備份容錯模型和一種多cpu熱備份容錯模型;然後進行了基於rtems操作系統的軟體容錯技術研究，提出了任務級容錯調度演算法以及基於檢查點技術的系統級容錯恢復機制和策略，同時研究了利用系統重注入進行軟體在線自修復的容錯技術;最後研究了基於fpga的部件級容錯技術，提出了對容錯模塊這一星載并行計算機關鍵部件的兩級容錯方案，實現該方案所需增加的電路少，可避免板級晶元以及fpga晶元內部任何邏輯發生單點故障。
  2. The reactive power compensation is an important engineering in the power system. the active reactive power compensator designed in this text takes the instantaneous reactive power theory of three - phase as foundation, and is formed by the reactive current testing circuit, current tracking control circuit and the main circuit, and among them the current tracking control circuit is formed by instruction current arithmetic circuit, current polarity checkout circuit and current tracking control logic circuit three parts in the circuit form

    無功功率補償是電力系統中的一項重要工程，本文所設計的有源無功功率補償器是以三相瞬時無功功率理論為基礎的，它由無功電流檢測電路、電流跟蹤控制電路和主電路三大部分組成，其中電流跟蹤控制電路由指令電流運算電路、電流極性檢測電路和電流跟蹤控制邏輯電路三部分構成。
  3. In data sampling circuit, high - speed, complex programmable logic device cpld technique is used. high - speed double - port ram, control sampling time sequence logic, cpu interfaces and bus circuit are implemented in cpld. sampling speed is up to 80mhz, sampling depth is ik - byte, and cpld can fulfill the requirement of the software arithmetic to sampling

    在數據採集電路中採用了高速復雜可編程邏輯器件cpld技術，晶元內設計有高速雙埠ram 、控制采樣時序邏輯及cpu介面、總線等電路，采樣速率高達80mhz ，采樣深度1k位元組，很好地解決了超聲波微位移傳感器軟體演算法對采樣的要求，並可實現在線升級，大大提高了系統的整體性能。
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