boundary scan test 中文意思是什麼
boundary scan test
解釋
邊界紹-
Standard test access port and boundary scan architecture
標準測試存取口及邊界掃描體系結構 -
Application of boundary scan technique to the design for board - level test
邊界掃描技術在板級可測性設計中的應用 -
Boundary scan aims at the test of application system, e. g. pcb test
邊界掃描測試是針對晶元的應用系統進行測試的，如pcb板測試。 -
A plan of design for test based of boundary scan testing is introduced for this signal processing system
接著，提出了該信號處理系統基於邊界掃描的可測性設計方案。 -
Jx5 microprocessor ’ s testing structure comprises built - in self - test ( bist ), boundary scan and internal scan
Jx5微處理器的測試結構由bist 、邊界掃描和內部掃描三部分組成。 -
In this paper, we combine the standard modules realize the boundary scan of estarl and also expand it to the test of internal circuit. this structure can save the i / o port of the chip and simplify the testing program
本文結合標準模塊設計實現了estar1的邊界掃描結構，並進行了擴展，應用到晶元內部測試，節約了測試i / o口消耗，簡化了測試過程。 -
In this paper we investigate and carry out boundary scan ^ internal scan and built - in self - test three dft technologies in the embedded microprocessor estarl and get satisfying result, the fault coverage is more than 96 %
本文針對嵌入式微處理器estar1的結構特點，研究並實現了邊界掃描、內部全掃描和內建自測試三種可測性設計技術，取得了良好的效果，故障覆蓋率達到96以上。 -
As one of the design for testability technology, boundary scan test ( bst ) fixes boundary scan cells between the device pins and core logics. thus, the bsc acts as the virtual test probe that carries out the test stimulus and captures the test response
作為一種結構插入的可測性技術，邊界掃描測試（ bst ）技術將邊界掃描寄存器單元安插在集成電路內部的每個引腳上，其作用相當于設置了施加激勵和觀測響應的內建虛擬探頭。 -
The majority of the test vectors are used to check the connection of the pins of the device. those vectors for connection test can be removed from the vector base for the device under test when deltascan is applied together with boundary scan test. the total vectors are therefore eliminated
測試矢量中大多數是用於測試引腳之間是否有短路或有引腳開路情況的，引入deltascan測試ic的引腳的開路和短路情況后，就可從xc5210 _ tq144的測試矢量集中去掉合併與短路，開路測試有關的測試矢量，進一步減少了邊界掃描所需的測試矢量。 -
In the logic design, the fundamentals and characteristics of ieee std. 1149. 1 specification and usb protocol are introduced first of all. according to altera ’ s fpga cyclone, it analyzes the architecture and jtag instructions of boundary scan test ( bst ). then the dissertation analyzes how to program cyclone device and offer the scheme of the design which is realized in verilog hdl by modelsim and quartus ii software
在介面邏輯設計中，首先分析ieee1149 . 1標準和usb協議，理解邊界掃描測試和usb數據傳輸的工作方式，然後針對altera公司的fpga器件cyclone ，通過分析它的邊界掃描測試結構和各種jtag指令，研究它的編程過程和編程特點，並提出設計方案。 -
In this thesis, the boundary scan technique is discussed in detail and a boundary - scan test system based on computer is also developed. the main contents can be summarized as follows : 1. the ieee std 1149. 1 boundary scan testing standard is researched, and the mathematical description model and some basic theorems of boundary scan testing process is analyzed subsequently
論文的研究內容及主要工作包括: 1 、對邊界掃描技術的基本理論和方法進行了分析和研究，並對邊界掃描測試過程中的數學描述模型以及邊界掃描測試的基本定理進行總結，為邊界掃描測試生成演算法的研究以及邊界掃描測試系統的開發奠定基礎。 -
So here introduces a new method - the combination of boundary scan with deltascan, in which deltascan is applied to do short and open test in ict, so that the number of vectors used to test circuit short and open in boundary can be eliminated. all vector test, including boundary scan test, need to create test vectors
任何邏輯元件的矢量測試，包括邊界掃描測試，都必須先生成測試矢量，然後用這些測試矢量作為輸入端的激勵信號，因此測試矢量是矢量測試的基礎，測試矢量生成方法的難易程度和測試矢量數目是邊界掃描技術能否在實際中應用的關鍵。 -
Test access port and boundary - scan architecture
測試存取口及邊界掃描結構 -
On the other hand, boundary - scan technique intelligent fault diagnostic method was applied to practice. for most digital system, devices with boundary - scan architecture are broadly used. only using four line or five line to connect pc parallel port with cut tap ( test access port ), all the ptvs can be loaded to cut and all homologous prvs can be taken back to intelligent fault diagnosis system
至於本文採用邊界掃描測試故障診斷技術，是考慮到本系統的通用性和簡潔性，因為對于大多數數字系統而言，具有邊界掃描結構的器件己廣泛應用，本文只需4條或5條信號線就能將pc機和被測邊界掃描電路連接起來，由此極大地簡化了智能故障診斷系統中為實現ptvs加載和prvs獲取而專門設計的介面板電路。 -
It is seen from the result of the experiment that pseudo exhaustive test with deltascan involvement is truly a simple and practical method to produce vectors for boundary scan, it is suitable for any kinds of boundary scan devices
從試驗結果可知，偽窮舉法與deltascan相結合的確是生成邊界掃描測試矢量的一個非常簡單實用的方法，適用於任何一種邊界掃描元件的測試矢量的生成。 -
For this purpose, we should employ the new test instrument fit for boundary - scan test
為此，我們必須為這些數字系統設計新的測試工具。 -
In this paper, ieee1149. 4 std mixed - signal test bus and its characteristic are studied. according to the structure defined in this standard, test methods of mixed - signal circuits are studied. the mixed - signal boundary - scan test system, which is complianted to ieee1149. 4 std, is designed
本文深入研究了ieee1149 . 4混合信號測試總線及其特點，並根據邊界掃描標準定義的測試結構對混合信號電路的測試方法進行研究，設計出符合ieee1149 . 4標準的混合信號邊界掃描測試系統。 -
In order to enhance the testability, reduce the maintenance costs of the electronic equipment, it is very important to develop a boundary - scan test system ( bsts )
隨著具有邊界掃描結構的晶元在裝備中的大量應用，開發出實用的邊界掃描測試系統，對于提高裝備的可測試性，降低維護和保障費用具有重要意義。 -
The main contents are as follows : the structure of mixed - signal circuit which newly - defined in ieee1149. 4 std is analyzed in detail, especially anolog boundary module and test bus interface circuit. on the basis of mixed - signal boundary scan technology, a scheme of mixed - signal boundary - scan test system is presented and the hardwares are implemented, including the controller and display unit
主要研究的內容以及所作的工作如下:詳細分析了ieee1149 . 4標準中針對混合信號電路測試新增的結構，即模擬邊界模塊及測試介面電路。基於混合信號邊界掃描技術標準，提出混合信號邊界掃描控制器的設計方案並實現了其硬體設計，包括邊界掃描控制模塊、顯示驅動模塊等。 -
As a design for test technology, the boundary - scan test fixes a special element called boundary - scan cell ( bsc ) between the device input pins and the core logic inputs, or between the core logic outputs and the device output pins
作為一種結構插入的可測性設計技術，邊界掃描測試技術將邊界掃描測試單元（ boundery - scancell ， bsc ）插在集成電路內部每一個輸入輸出引腳上。
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