bus timing 中文意思是什麼

bus timing 解釋
總線定時
  • bus : n （pl busses buses）1 公共馬車；公共汽車；客機。2 〈口語〉汽車，機器腳踏車；飛機。3 【電學】信息...
  • timing : n. 1. 時間選擇。2. 定時，校時，計時，調速。3. 【自動化】同步；時限。
  1. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  2. Its premise is pci bus specification and its sticking point is to analysis the function and architecture of pci bus controller. this dissertation finishes the design of pci bus controller, and it has also completed the function simulation of this module as well as timing simulation and a pcb card for test which prove it rightness at last

    通過本論文的研究，完成了pci總線控制器的設計，並且通過編寫測試激勵程序完成了總線控制器功能模擬，以及布局布線后的時序模擬，並設計了pcb實驗板進行了測試，證明所實現的pci目標控制器完成了要求的功能。
  3. It has been playing an important role in equipping all kinds of arms and services for campaigns, tactical exercises and emergent actions etc. based on the detailed analysis of the exchange ' s architecture and implementing, this thesis points out some disadvantages of the device, such as too many absolute components, not very high enough reliability and security, very large size and weight, operating and maintaining difficultly. considering low power requirement and man - machine interface optimizing design at the same time, the thesis come up with an integrated design scheme to the previous device based on " mcu + cpld / fpga architecture " : ( 1 ) signal frequency dividing, timing frequency producing, 20 customers " led states controlling are implemented in cpld ; ( 2 ) decoding, latching data and controlling signals are implemented in cpld by bus interface between mcu and cpld ; ( 3 ) chip selecting principles and mcu idle mode design are completed under the consideration of low power requirement ; ( 4 ) operation by chinese lcd menus is adopted in the man - machine interface

    本項目以該交換機為研究對象，在詳細分析原設備的系統結構和功能實現方式的基礎上，指出該機型在使用過程中存在技術相對陳舊、分立元件過多、可靠性和保密性不夠、體積大、重量大、維修困難等問題，同時結合系統的低功耗需求和優化人機介面設計，本文提出基於「單片機+ cpld fpga體系結構」的集成化設計方案：在cpld中實現信號音分頻和計時頻率生成電路、 20路用戶led狀態控制電路； cpld與單片機以總線介面方式實現譯碼、數據和控制信號鎖存功能的vhdl設計；基於低功耗設計的器件選型方案和單片機待機模式設計；人機介面的lcd菜單操作方式。
  4. System control module accomplishes many functions, such as systemic initialization, controling work of the system, man - machine interface and selecting channel. it communicates with other modules by i2c bus. timing signals are inputed into microprocessor through p1 port and control signals are provided through p2 port

    系統控制模塊和其他模塊間的通訊基於i ~ 2c總線，並利用了p1口進行各時鐘信號的檢測和利用p2口的各線作為控制線宋控制相應模塊的工作。
  5. On the other hand, the design of the software is complex, and it needs strictly correct timing diagram, which is because of the brief application of the hardware of 1 - wire bus network

    本文對單總線主機端介面器件進行了可行性方案研究，並對單總線軟硬體設計及其在設計中遇到的問題做了詳細的描述。
  6. A frequency conversion timing control system for constant pressure water supply based on lonworks field bus

    現場總線的恆壓供水變頻調速系統
  7. In can - bus communication technique, the circuit design method of can - bus node and the technique of structuring distributed can - bus controlling network are put forward, how to realize can calling and broadcasting communication under pelican mode is explained thoroughly, and the computational technique of bit - timing parameter of can controller sja1000 is detailed

    在can總線通信技術中，給出了can總線節點電路的設計方法和基於can總線的分散式控制網路的組建方法，詳細論述了增強模式下can總線分散式控制網路實現點名和廣播通信的原理與方法，深入探討了can控制器sja1000位定時參數的計算方法。
  8. The fourth chapter introduces the circuit design method of can - bus node, as well as the technique of structuring distributing - type can - bus measuring and controlling network, explains thoroughly how to realize can calling and broadcasting communication under pelican mode, and discusses detailedly the computational technique of bit - timing parameter of can controller sja1000. the latter part of this chapter points out several important problems confronted and solved by the author in the course of designing can - bus communication system

    第四章介紹了can總線節點電路的設計方法和基於can總線的分散式測控網路的組建方法，詳細論述了增強模式下can總線分散式測控網路實現點名和廣播通信的原理與方法，深入探討了can控制器sja1000位定時參數的計算方法，總結了作者在設計can總線通信系統的過程中遇到和解決的幾個關鍵問題。
  9. The bulk of the book concentrates on details important to reliable, worst - case - scenario microcontroller hardware design, like bus loading, timing, and the use of i / o, dma, and interrupts

    大部分的書集中在重要的細節，以可靠，最壞的情況-情景單片機硬體設計，像公共汽車上落，時間和使用的i / o ， dma的，而中斷。
  10. Microprocessor system bus - 8 - bit and 16 - bit data multibus i. functional description with electrical and timing specifications

    微處理器系統總線. 8位和16位數據多路總線i .第1部分:電氣和定時規范功能描述
  11. Further boosting pci - x performance will be many other tweaks that improve reliability, timing and scalability of the bus

    將來還有許多可改進之處，改善該總線的可靠性、時序和可擴性，來進一步提高pci - x的性能。
  12. Microprocessor system bus i, 8 - bit and 16 - bit data - part 1 : functional description with electrical and timing specifications

    微處理機系統總線i 8位及16位數據第1部分:電氣與定時規范的功能說明
  13. This dissertation finishes the design of pci bus target controller, with vhdl description of register transfers level. and it has also completed the function simulation as well as timing simulation after placing & routing. a fpga on pcb board is designed to test the target controller and the result of test meets basal function demand

    本論文完成了pci總線目標設備控制器的設計，採用vhdl對其進行了rtl級的描述，並且通過編寫測試激勵程序完成了功能模擬，以及布局布線后的時序模擬，通過fpga在pcb實驗板上進行硬體模擬，證明所實現的pci目標設備控制器符合基本功能要求。
  14. The misc logic module can capture and lock the errors of processor local bus and on - chip peripheral bus. these errors can be shown by light - emitting diode light. the chipscope _ ila core is used for debugging the fpga logic and timing

    而輔助邏輯主要是用來捕獲並鎖定powerpc ~ （ tm ） 405的處理器局部總線（ plb ）和片上外圍總線（ opb ）的錯誤，並通過led燈進行顯示。
  15. Besides, for servo control tache, an simple and credible 1c is applied to little power dc servo control system in order to realize a closed - loop position control system. ^ ^ finally, the latest wdm device driver ' s theory in windows98 / 2000 operation systems are discussed on the basis of analyzing the system structure of these platforms. a concrete realizing method of wdm about how to manage bottom hardware and real - time control by for pci and usb bus are given in detail, which resolves the timing gathering data and communication in win32 environment for the system of computer ' s measure and control

    最後，在剖析windows98 / 2000體系結構的基礎上，系統地討論了最新的wdm設備驅動程序的運行原理，詳細給出了wdm設備驅動程序在基於pci 、 usb總線的測控系統中的底層硬體管理和實時控制的具體應用，解決了在win32環境下測控系統中重要的實時數據採集和數據通訊等問題。
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