chip architecture 中文意思是什麼

chip architecture 解釋
晶片結構
  • chip : n 1 碎片，削片，薄片；碎屑；薄木片；無價值的東西。2 （陶器等的）缺損（處）。3 （賭博用）籌碼；〈p...
  • architecture : n. 1. 建築學。2. 建築（樣式、風格）；建築物。3. 構造，結構；【自動化】（電子計算機的）架構，體系結構。
  1. The chip simulation network laboratory system this paper disguessed is a distribute network simulation system based on lan. the system ' s architecture is a c / s of three lays. the front platform are the chip simulation network system application program terminer ; the middle lay is a dcom server, it ' s duty is to deal with the communication and data transmission between the terminer and then database server, and to execute the logical operation. the application program just connect with the middle lay and get data from it, the connection and operation with database server will be managed by the dcom server. the duty of database server is to access and backup the final data

    具體是由位於網路各個終端的晶元模擬網路實驗系統應用程序為前臺；中間層為dcom應用程序服務器，負責處理前臺應用程序與后臺數據庫的通信和數據傳輸，並執行業務邏輯，前臺應用程序只需要與應用程序服務器建立連接，在中間層操作數據即可，與后臺數據庫的連接和操作由應用程序服務器來統一管理操作。后臺數據庫只負責數據的存取操作。本論文實施的晶元模擬網路實驗系統模擬了主要的邏輯電路器件， 8088cpu ，存儲器，寄存器，數據總線，地址總線和控制總線，及其它相關晶元。
  2. Cryptogrammic chip introduced in this paper has been tested on the altera ' s apex20ke fpga. the main clock frequency reached 40mhz. the chip includes 30, 000 les. in order to utilize esb resource in altera ' s chip, we adopted embedded rom and ram and can realize the function of whole system with only one chip. lt is the embodiment of methodology and notion of sopc ( system on a programmable chip ). the simulation of this cryptogrammic chip proves the correctness of function of the chip, which shows that the important ideology based reconfigurable architecture has special significance in designing of cryptogrammic chip

    本文所闡述的密碼晶元在altera公司的apex20kefpga上進行了測試。工作頻率達到了40mhz ，佔用了3萬個le . ，利用altera器件的esb資源，採用內置ram和內置rom設計方法，用一片晶元即可實現整個系統的功能，充分體現了sopc的設計方法和理念，對晶元的模擬和測試均證明晶元功能正確，表明基於可重組體系結構這一重要思想在密碼晶元設計中具有特殊的意義。該晶元的設計遵循hdl設計方法學的一般方法。
  3. This paper systematically presents the whole design process of a cryptogrammic chip based on reconfigurable architecture. firstly it begins with a brief introduction to the background of the cryptogrammic chip design, and it clearly states the characteristic and the researching thoughts of cryptogrammic chip design with hdl. then the design environment and cipher algorithms are introduced briefly

    本文系統地論述了基於可重組體系結構的密碼晶元設計的全過程，文章首先闡述了該設計的課題背景，給出了使用hdl方法設計密碼晶元的特點和研究思路，然後對晶元的設計環境作了簡要說明，並對密碼演算法進行了簡單介紹。
  4. Prior to google, alan spent 15 years at digital compaq hp s western research laboratory where he worked on a variety of chip design and architecture projects, including the microtitan floating point unit, bips the fastest microprocessor of its era

    在他加入google之前， alan在digital compaq hp的西部研究室工作了15年，致力於各種晶片的設計及製造專案，其中包括當時最快的微處理器： microtitan floating point unit ， bips 。
  5. It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ), 5 - stage pipeline, hardware multiplier and divider, interrupt controller, 16 - bit i / o port and a flexible memory controller. new modules can easily be added using the on - chip amba ahb / apb buses. it has flexible peripheral interfaces, so can be used as an independent processor in the board - level application or as a core in the asic design

    它遵照ieee - 1745 （ sparcv8 ）的結構，針對嵌入式應用具有以下特點：採用分離的指令和數據cache （哈佛結構） ，五級流水，硬體乘法器和除法器，中斷控制器， 16位的i / o埠和靈活的內存控制器，具有較強的異常處理功能，新模塊可以輕松的通過片上的ambaahb / apb總線添加。
  6. It includes chip selection, schematic circuit design, cpu selection and configuration, startup of the system, selection and configuration of embedded operation system, selection and configuration of tcp / ip software. it also describes some driver programming techniques of network controller. part 3 ( chapter 5 and 6 ) briefly introduces encryption technology and the ipsec protocol system, including architecture, mode, security association, security policy, implementation mode, processing of in / out packet, esp ( encapsulation security payload ), ah ( authentication header ), ike ( internet key exchange ) etc. the security requirements of embedded - networking is also analyzed

    本文首先探討了嵌入式網路的原理和設計要求，接著介紹了本文所開發的嵌入式系統的硬體平臺的設計（包括處理器的選擇與配置、存儲器的選擇和io設備的選用等） ，系統的啟動（包括bios和dos的啟動以及嵌入式操作系統vrtx的配置和引導） ，網路及其安全服務的實現（包括嵌入式協議棧usnet的選取、底層驅動程序的設計和安全協議ipsec的分析與實施） 。
  7. Integrated circuit design has entered into the era of system on chip ( soc ), the bus interconnect architecture of system on board have also developed into a kind of hierarchy architecture - on chip bus ( ocb )

    隨著集成電路設計進入到系統晶元（ soc ）時代，板極系統的總線互連結構也發展成為系統晶元的層次化總線體系一片上總線。
  8. With turning the scale of asic ( appl ication specified integrated circuits ) to s0c ( system on chip ), which conunon1y is composed of mcu, specified function ip cores, memory, periphery interface etc, the ip reuse techno1ogy is very important in s0c design flow, which can realize the constructions of different levels components. the approach of configurable system, method and design f1ow for udsm ( u1tra deep sub micron ) asic, logic system design using hdl 1anguage, coding style, static and dynamic verification strategy are a1so presented in chapter 2. in chapter 3 we study the vlsi - - dsp architecture design, dense computation and high speed high performance digital signal processing unit structure, which includes high speed mac components and distributed arithmetic unit

    在工程設計方法及結構化設計和高層次綜合的研究中，介紹了在深亞微米工藝條件使用的方法和asic設計流程，討論了高層次綜合的核心如何從描述推出電路構成的設計思路，針對不同目標的設計技巧討論了採用hdl語言進行邏輯系統設計的方法，給出了用vhdl語言進行代碼設計時的規范和風格，在面向soc的驗證策略討論了動態和靜態的驗證技術，提出了進行單獨模塊驗證、晶元的全功能驗證和系統軟硬體協同驗證的整體策略。
  9. Superscalar risc microprocessor is the further development of reduced instruction set computer, it improve the instruction - level - parallism by means of adding parallel pipelining function units and dynamic on - chip scheduling. this thesis anslysises the architecture and the diversified techniques of superscalar computer

    超標量risc微處理器是精簡指令結構（ risc ）的進一步發展，它通過增加并行流水執行單元並結合片上硬體動態調度來提高指令并行度。
  10. In the paper, an automatic macro - cell routing system, which bases on the architecture of three levels : chip, macro - cell and transistor group, is discussed

    本文基於晶元、宏單元、晶體管群三級的層次化架構，實現了一個宏單元自動布線系統。
  11. Traditional methods such as emulation can do little about it, it has to introduce some new arts. on the path of modern computer and cpu designing, the registers, level 1 cache, level 2 cache on the chip and level 3 cache on the mainboard, plus ram, hard disk or floppy disk or flash disk, make up of the modern multi - hiberarchy storage architecture

    現代計算機和cpu設計中， cpu片內的寄存器、一級高速緩存（ level1cache ）和二級高速緩存（ level2cache ） ，主板上的三級高速緩沖，再加上主存，外存（硬盤、軟盤、電子盤等） ，構成了現代計算機的多級存儲體系結構。
  12. The chip is accomplished in the full cooperation with other team members, the author pays particular attention to the analysis of the whole chip architecture and three sub - block design : transconductance amplifier ( ota ), voltage reference and current reference. based on existed technologies, a new high order temperature compensated voltage reference and a creative current reference with high order temperature compensation are shown respectively. the author simulated all the sub - block and whole chip by hspice

    該晶元的設計是由小組成員共同完成，本人主要負責了總體電路的分析、聯合模擬驗證及以下三個子電路的設計: 1 、跨導放大器，詳細分析了bandgap跨導放大器輸入級的動靜態特性及其優缺點，並結合系統要求，設計了一種與cmos工藝相兼容、可替代bandgap跨導放大器的低壓共源共柵跨導放大器。
  13. Firstly, we present the conception and technology of software reuse, then deeply discuss key technologies of software reuse such as software component technology, software architecture and domain analysis, etc, whose software component, i. e. software chip, is the main part of software reuse ; software architecture is software framework, which can been reused as software framework of a large granularity and higher abstract level and offers the fundament and the context for component integration ; domain analysis concentrates on a special application domain so that the generality of the design of software component is not considered in wide range, meanwhile its ratio of the reuse increases

    本文首先敘述了軟體復用的概念和軟體復用技術，然後深入探討了軟體構件技術，軟體體系結構和領域分析等軟體復用中的關鍵技術，其中軟體構件技術（即軟晶元）是軟體復用的核心；軟體體系結構是軟體的骨架，可以作為一種大粒度的、抽象級別較高的軟體體系結構進行復用，並能夠為構件的組裝提供基礎和上下文；領域分析使軟體復用的目標集中在一個特定應用領域內，使構件的製作不需要在很廣的范圍內考慮其通用性，構件的復用率也相應增大。
  14. Processor _ architecture : lists the processor ' s chip architecture

    列出了處理器的晶元架構。
  15. The name of the common chip architecture for ibms pseries and iseries servers

    Ibm的pseries和iseries服務器通用晶元體系結構的名字。
  16. In this survey we explore the hardware aspects of reconfigurable computing machines, from single chip architecture to multichip systems, including internal structure and external coupling

    在某一時刻一條指令執行過程中整個處理器的部件都服務于盡快完成這條指令，至少在概念上如此。
  17. The pssc superchip, a single - chip implementation of the power2 s eight - chip architecture, powered the 32 - node ibm deep blue supercomputer that beat world champion garry kasparov at chess in 1997

    Pssc超級晶元是power2這種8晶元體系結構的一種單片實現，使用這種晶元配置的一個32節點的ibm深藍超級計算機在1997年擊敗了國際象棋冠軍garry kasparov 。
  18. In terms of reliability, another advantage of this approach is that if copies of the sub - job are sent to machines with different architectures, we can protect ourselves against potential errors introduced by a chip architecture, operating system or compiler

    從可靠性來講，這種方法的另外一個優點是，如果子任務的不同拷貝被發送到不同架構的機器上，我們就可以避免由於一種晶元架構、操作系統或編譯器而引起的潛在錯誤。
  19. 10 wallner s. a configurable system - on - chip architecture for embedded devices. in ninth asia - pacific computer systems architecture conference acsac 2004, beijing, china, springer, lncs 3189, sept. 7 - 9, 2004, pp. 58 - 71. 11 wallner s. design methodology of a configurable system - on - chip architecture

    它結合了大量的宏模塊資源，包括一個類標量處理器內核粗粒度可配置的處理陣列嵌入式的存儲器，以及由微任務控制器mtc監控的定製模塊。
  20. At light loads, the architecture allows the chip to “ skip ” cycles to reduce power dissipation. in the circuit design, the basic principle and small signal model of the boost power stage are given at first, and then the stability and small signal model of the control loop are also analyzed, finally, the whole chip architecture and sub - block parameters are presented according to the application requirements

    在電路設計中，首先闡述了升壓型直流轉換器的功率輸出級的拓撲結構、基本原理、小信號模型，然後分析了電流模式控制迴路的穩定性及小信號模型，最後根據應用要求進行了電路的總體架構設計，完成了每個子電路的各種參數的分析、計算。
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