clock delay 中文意思是什麼
clock delay
解釋
延時機構-
After loading there was a long delay before the horses were brought, these having been unharnessed during the ridding ; but at length, about two o clock, the whole was under way, the cooking - pot swinging from the axle of the waggon, mrs durbeyfield and family at the top, the matron having in her lap, to prevent injury to its works, the head of the clock, which, at any exceptional lurch of the waggon, struck one, or one - and - a - half, in hurt tones
東西裝上車以後，她們又等了許久，拉車的馬才備好了牽過來，因為馬車到了以後，馬就從車上卸下來了一直耽誤到兩點鐘，人馬才一起上路做飯的鍋吊在車軸上，德北菲爾德太太和孩子們坐在馬車頂上，把鐘放在腿上抱著，防止馬車在猛烈顛簸時把機件震壞了馬車猛地晃一下，鐘就敲一下，或敲一下半。 -
The clock recovery block of usb2. 0 transceiver macrocell consists of phase locked circuit, such as pll and dll ( delay locked loop ). this block use external crystal 12mhz sin signal to produce 60mhz, 120mhz, 480mhz clock signal, and can recover colock signal form date wave. it can support 480mbps ( hs ) and 12mbps ( fs ) word speeds as defined in usb2. 0 specification.
目的是用鎖相環電路? pll和dll （延遲鎖相環）實現usb2 . 0收發器宏單元utm的時鐘恢復模塊。其中pll環路構成的時鐘發生器將外部晶振的12mhz正弦信號生成60mhz 、 120mhz 、 480mhz等本地時鐘信號。 dll環路依據本地時鐘信號對外部數據信號進行時鐘恢復。 -
Abstract : a new clock - driven eco placement algorithm is presented for standard - cell layout design based on the table - lookup delay model. it considers useful clock skew information in the placement stage. it also modifies the positions of cells locally to make better preparation for the clock routing. experimental results show that with little influence to other circuit performance, the algorithm can improve permissible skew range distribution evidently
文摘:提出了一種新的時鐘性能驅動的增量式布局演算法，它針對目前工業界較為流行的標準單元布局，應用查找表模型來計算延遲.由於在布局階段較早地考慮到時鐘信息，可以通過調整單元位置，更有利於后續的有用偏差時鐘布線和偏差優化問題.來自於工業界的測試用例結果表明，該演算法可以有效地改善合理偏差范圍的分佈，而對電路的其它性能影響很小 -
This logic is designed containing input signal delay, event type classification, event pre - scaling and timing logic and works in pipeline mode under control of 20mhz clock which ensures no dead time contribution
主觸發邏輯在20m時鐘下以流水線的方式工作，保證沒有死時間的產生。第二個例子是任意數字信號發生器的設計。 -
It will delay the start signal for six clock periods.
它將起始信號延遲六個小時周期。 -
In digital circuits, an outer rc circuit, combined with inter ring oscillator obtain series of oscillation pulses for system clock and delay clock
在晶元的數字電路中，設計了外部rc環節配合片內環振構成的振蕩電路，提供系統時鐘、延遲時鐘的振蕩脈沖。 -
This module works with a clock of 40mhz and its input accept lvds signal, output are both in lvds and ecl standard. the setting of the delay parameters is realized with vme software commands
該插件的工作由40mhz時鐘控制，輸入電平為lvds 、輸出為lvds和ecl電平，其初始化通過vme總線加載，並具有多種編程下載方式。 -
4. through using the concept of logic balance, a high performance telecommunication switch network test chip is accomplished by using xilinx virtex 300e - 6 and the working clock frequency is up to 125mhz. this chip can give an exact test for the network delay time, throughput, network delay time dither, rate of errors and lost data
4 ）結合邏輯平衡的思想，採用xilinxvirtex300e - 6器件，為一家著名的通訊技術有限公司設計了速度達125mhz的交換網測試晶元，能夠對交換網的吞吐率，網路延時，網路延時抖動，數據包錯誤率，包丟失率等進行嚴格的測試，並根據當前網路的流量大小自動調節網路負載。 -
Due to the concern of process variation, the delay of each clock buffer is treated as a range instead of a single value
在製程變異上面，每個時鐘緩沖器的延遲值被表示為一個范圍值。 -
As to phased array receiving, a scheme of separating the delay clock and sampling clock is explicated, which effectively enhance the phased receiving delay resolution
對于相控接收延時，本文闡述了一種將延時時鐘和采樣時鐘分離的方案，有效地提高了接收延時解析度。 -
This article sets forth the orientation theory of digital television and radio signals ' space position, speed, clock error and etc. and then analyses the error, troposphere delay, multipath and shelter domine effect, relying on the creation of hypodistance arithmatic model and the deduction of calculation formulae
摘要文章通過建立偽距數學模型，推導整理出計算公式，從而對數字電視廣播信號的空間位置、速度和時鐘偏差等參數的定位原理進行了闡述，最後對誤差、對流層延遲、多徑和遮擋效應等進行了分析。 -
A lot of applications in broad bandwidth ip network are based on non - real - time communication by comparison with atm. we present dynamic virtual rate scheduling policy and limited difference - of - clock hybrid packet scheduling. they do n ' t only guarantee upper bound of traffic delay that is equal to vc and wfq ' s, but also optimize non - real - time communication by way of preventing real - time traffic from unfairly engaging network resource
相對atm網路，寬帶ip網路中有大量的網路應用以非實時通信為基礎，本文提出了動態虛速率調度策略和有限時鐘差混合包調度演算法，與vc 、 wfq等調度演算法相比，不僅同等地確保實時通信的最小時延上界，而且通過限制實時通信對網路資源的不合理佔用，使得實時通信和非實時通信公平合理地共享網路資源，優化了非實時通信的轉發性能，改善了網路資源的有效利用率。 -
The implementation of in - chip clock generator is often based on modern cmos ic process technology which is usually adopted by very large scale digital system. while designing a deep sub - micrometer cmos circuit, delay, power consumption and die size are of the main factors that must be considered
使用現代深亞微米cmos集成電路工藝製造的內部時鐘發生器要綜合考慮延時、功耗、面積等各種重要因素，而且經常要針對soc系統的需求設計特殊的電路結構。 -
By careful selection of the ratio between this resistor and the integrating resistor ( a few tens of ohms in the recommended circuit ), the comparator delay can be compensated and the maximum clock frequency extended by approximately a factor of 3. 3
通過小心選擇這個電阻和積分電阻之間的比值（在推薦線路里，大約是數十歐姆） ，比較器的延遲就可能被補償，最大的時鐘頻率可近似延伸到3 . 3倍。 -
Whenever a request for time check is received from the user s computer, the hko internet time server will return a time message based on the hong kong standard time. the user s computer then uses the received time message and the time delay in receiving the return message to adjust its clock
當天文臺網際網路時間伺服器收到使用者電腦發出要求對時的信息后，伺服器便會傳送香港標準時間的信息至使用者電腦，該電腦會根據收到的時間信息及傳送時間來校準時鐘。 -
The difference clock delay match technology adjusts the two channel ad analog clock phase and implements the two way ad uniformly - space sampling
差分時鐘延遲匹配技術通過對兩路ad的采樣時鐘進行相位調整，實現了兩路ad的等間隔采樣。 -
We have purchased permission to waive the usual delay ; and at half - past two o clock the mayor of marseilles will be waiting for us at the city hall
我們已經付了結婚預告費，兩點半的時候，馬賽市長就會在維麗大酒家等候我們。 -
Warning : circuit may not operate. detected 4 non - operational path ( s ) clocked by clock clk with clock skew larger than data delay. see compilation report for details
這個問題好象比較嚴重，幫我看看，你遇到過沒有，他說不能正常工作了？
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