clock digital 中文意思是什麼

clock digital 解釋
嚙合器總成
  • clock : n 1 鐘；掛鐘，座鐘，上下班計時計。2 〈俚語〉記秒錶，卡馬表；〈美俚〉〈pl 〉駕駛儀表，速度表，里程...
  • digital : adj. 1. 手指的；指狀的。2. 數字的，數據的。n. 1. （鋼琴等的）琴鍵。2. 手指。
  1. The esd scheme is one of the flagship e - government projects under the " digital 21 " it strategy. the esd web site is an innovative one - stop - shop portal providing integrated electronic public and commercial services round the clock

    公共服務電子化計劃是資訊科技及廣播局在數碼21資訊科技策略下的一個電子政府旗艦項目。
  2. Automatic test pattern generation for multi - clock digital system based on s amp; amp; cct

    基於安全充分捕獲技術的多時鐘數字系統測試矢量生成
  3. Inside the instrument has many kinds of scaling conversation formula which can carry out chosen scale conversation such as convert into length etc. digital clock timer wide use to clocking, timing in every industry field. it is operate brief, clocking accuracy, timing alarm, and with outer connected start stop, clear function

    本表含有前述智能流量積算控制儀的全部功能，增加了獨特的防盜措施，提高了系統的安全性，即使在斷電的情況下，亦可有效地防止盜用，保證了用戶的準確計量使用，且操作簡便，可靠性高。
  4. A real - time digital clock initially synchronizing with the timeserver provided by the hong kong observatory will be displayed on the ets screen for tender submission indicating the system date and time

    電子投標系統的標書投遞屏幕初時會顯示與香港天文臺提供的時間伺服器顯示同一時間的實時電子時鐘，以顯示該系統的日期和時間。
  5. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  6. The analog signals are regulated to satisfy the system and analog - to - digital converter ( adc ) ; dsp is the core part and is connected with adcs, a controller of ethernet, a rs - 485 bus transceiver, a can bus transceiver and a clock. the real - time data is disposed by dsp and is transferred to the upper computer when the alarm is happened

    模擬信號調理模塊對輸入的信號進行調理，以達到系統和模數轉換器（ adc ）采樣的要求; dsp作為系統的核心部件，外擴了adc 、以太網控制器、 rs - 485總線收發器、 can總線收發器和時鐘晶元， dsp對實時數據進行處理，當報警發生時將實時數據通過以太網上傳給上位機。
  7. In this paper, the design of a specific chip for circuit emulation based on ip is put forward and realized and the main functional modules and the key algorithms including an all - digital adaptive clock recovery method and a dynamic depth buffer algorithm are described in detail

    文章根據相關標準提出並實現了一種電路模擬專用晶元的設計方案，並對其中主要功能模塊和關鍵演算法作出了詳細說明，包括一種全數字的自適應時鐘恢復方法、動態深度緩沖演算法等。
  8. Founded in 1993, shenzhen chaowei industry co., ltd. a professional manufacture, engaging in lcd clock, mini phone, am fm radio, digital recorder, practical electric gifts and quartz clock core. with the franchise of import and export, chaowei is also a permanent member of shenzhen clock watch association

    深圳市超維實業有限公司成立於1993年，是lcd鐘迷你電話機am fm收音機數碼錄音機實用電子禮品和贈品及石英鐘機芯的專業製造商，是深圳市鐘表行業協會的常務理事單位，擁有自營產品進出口權。
  9. Realization of digital clock control system by complex programmable logic device

    實現的數字鐘控系統
  10. It ' s very convenient to use a scm to design a digital clock with software

    摘要用單片機來設計數字鐘，軟體實現各種功能比較方便。
  11. The third, the whole circuit of digital cmos image sensor is presented. the circuits of pixel array, clock signal generator and sam have been improved on the base of simulation

    再次，我們對整個cmos數字圖像傳感器進行了電路設計，主要包括：時鐘信號發生器，順序移位寄存器和像素陣列。
  12. Of course the sampling clock is itself a digital signal

    時鐘本身也是數字信號，也會干擾模擬電路。
  13. It had also used vhdl language to carry through the timing simulation about hvct and digital clock. the simulation had the same result to the theory. it had established stability foundation to the future chip simulation

    並以實際應用為例，用其對高壓電流互感器和數字鐘進行了時序模擬，模擬結果與理論一致，為進一步的晶元模擬奠定了堅實的基礎。
  14. The paper uses the surface radiation observations from 08 to 17 o ' clock and the visible, infrared digital cloud picture from gms4 at the same time over beijing, tianjin, jinan, taiyuan, hefei, nanjing, shanghai area in june and july 1994

    本文利用1994年6月、 7月北京、天津、濟南、太原、鄭州、南京、合肥、上海地區地面凈輻射觀測資料及同期gms衛星紅外、可見光數字雲圖資料。
  15. Single frequency source is usually used as local oscillator in communication system and radar system, also as a reference clock in digital circuits, so it is a extensive - applied technique

    固定頻率源可以在在通訊系統和雷達系統中作為本機振蕩器，也可以作為數字電路的基準時鐘信號，因此得到了廣泛的應用。
  16. Spb time is the one that would support the replacement of the skin pocket pc clock tool software analog and digital clock protocol, the long - time, timer, hutchison and stopwatch functions when combined

    2 . 85 mb spb time是一款應可以支持更換皮膚的pocket pc時鐘工具軟體，模擬和數字時鐘制式，多時區時間顯示，定時器，記時和秒錶功能相結合
  17. This paper based on control theory, according to the conception of phrase lock loop and direct digital synthesis, we designed the clock circuit. it realizes the amalgamation of kinds of the ways about clock, which make it has some superiority

    本論文在控制理論的基礎上，以鎖相頻率合成和直接數字頻率合成作為設計思想，搭建時鐘控制電路，在業界實現了多種時鐘控制電路實現方法的融合與統一，具有一定的優越性和領先性。
  18. Digital clock management system and its application

    數字時鐘管理系統及其應用
  19. Varification regulation of standard digital clock

    標準數字時鐘檢定規程
  20. Digital clock timer segment timer

    數字時鐘定時器分段定時器
分享友人
分享到 Line

分享到臉書