clock-reset 中文意思是什麼

clock-reset 解釋
時鐘復位
  • clock : n 1 鐘；掛鐘，座鐘，上下班計時計。2 〈俚語〉記秒錶，卡馬表；〈美俚〉〈pl 〉駕駛儀表，速度表，里程...
  • reset : vt n 重新安放，重新安裝；重排（鉛字）；重鑲，重嵌（寶石）；重磨（刀具等）；【電訊】重調，重安設；...
  1. In this paper, it is shown that some atomic formulas of symbolic states generated by the algorithms can be removed to improve the model checking time - and space - efficiency. such atomic formulas are called as irrelevant atomic formulas. a method is also presented to detect irrelevant formulas based on the test - reset information about clock variables

    一個時間自動機是一個五元組n ， l 0 ， c ， e ， i ，其中n為一個有窮的位置集合， l 0n是初始狀態， c是一個取實數值的時鐘變量的有窮集合， e ng c 2 cn是轉換的集合。
  2. If you are travelling to a destination several time zones away, you will probably experience jet lag as the body internal circadian clock is only able to reset itself at a rate of about 1 hour per day

    如您于飛行旅途中須橫越多個時區time zone ，您有可能因身體內在時鐘又稱生物鐘無法適應外在時間突變，而衍生飛行時差反應。
  3. Press clock button to reset the time set mode. the auto or manu reception mode returns

    按clock按鈕使時間設置方式復位，變成自動或人工接收方式。
  4. Winchell has to hurry. the clock will start as soon as the ball is reset

    溫切爾要抓緊時間了球一放好，表就開始計時了
  5. An improved high - resolution current - mode sorter is presented. its structure complexity is o ( n ), which is crucial to the expansion of its size, and its dynamic range is large. only one clock signal and one reset signal are needed. no biasing signal is required. the operation point is constructed according to the input current, so it is self - adaptive, which is very important for an all - purpose component. in average value circuit, subtraction circuit, winner - take - all ( wta ) circuit and control circuit, it has good performance even at a large input current. this sorter has high precision, high resolution and low power, as has been proved via hspice simulation. it can be implemented in the standard digital cmos technology and widely used in many fields, so it is of great value in applications

    提出了一種改進的高精度電流型排序電路.它的結構復雜性僅為o （ n ） ，便於擴展;動態范圍大;它是自適應的，工作點由輸入電流確定，故不需要偏置信號，這對作為通用器件使用的排序電路來說是很重要的.通過利用平均值電路、減法電路、 wta電路和控制電路，可以使該電路在大輸入電流下依然保持高性能. hspice模擬表明該電路具有高準確性、高精度、低功耗的特點.它能用標準數字cmos工藝來實現，可以被應用於很多領域，具有很高的應用價值
  6. The hardware system includes power supply circuit, clock reset circuit, jtag model building circuit, decoding circuit, memory interface circuit, man - machine interface circuit and numeric control constant - current source interface circuit

    硬體系統主要包括電源電路、時鐘復位電路、 jtag模擬介面電路，譯碼電路、存儲器介面電路、人機介面電路、 adc轉換電路和數控恆流源介面等。
  7. The cloning process also appears to reset the “ aging clock ” in cloned cells, so that the cells appear younger in some ways than the cells from which they were cloned

    復制過程似乎也會重新設定復制細胞的老化時鐘，所以這些復制的細胞，在某些方面似乎比原來的細胞要來得年輕。
  8. An idea is brought forth to design the total structure of the usb interface ip, the main control logic, the mcu interface ( the function is the same as the pdiusbd12 chip of the philips semiconductor ) and a dpll which is used to synchronize data and separate the clock. this paper also introduces packet recognition, transaction sequencing, sop, eop, reset, resume signal detection / generation, nrzi data encoding / decoding and bit - stuffing, crc generation and checking ( token and data ), packet id ( pid ) generation and checking / decoding,

    提出設計了usb介面電路的整體構架，設計了usb的主要控制邏輯和與mcu的互連的介面（此介面與飛利普的usb介面晶元pdiusbd12兼容） ，也設計了一個數字鎖相環（ dpll ）來同步數據和分離時鐘，並對同步模式的識別、并行/串列轉換、位填充/解除填充、 crc校驗/產生、 pid校驗/產生、地址識別和握手評估/產生做了具體的分析。
  9. At the same time, this paper presents packet recognition, transaction sequencing, sop, eop, reset, resume signal detection / generation, clock / data separation, nrzi data encoding / decoding and bit - stuffing, crc generation and checking ( token and data ), packet id ( pid ) generation and checking / decoding, serial - parallel / parallel - serial conversion

    對同步模式的識別、并行/串列轉換、位填充/解除填充、 crc校驗/產生、 pid校驗/產生、地址識別和握手評估/產生做了具體的分析。
  10. At the same time the clock chip pcf8563 and serial eeprom chip csi24c01 with reset and wdt circuit of i2c bus are used hi the system. they have not only provided the non - volatility data storage area, the supervision ability of power supply and mcu and the rtc, and its i2c bus structure has been simplified the circuit design

    同時在系統中還使用了護c總線結構的時鐘晶元pcf8563和內置reset 、 wdt電路的串列eeprom晶元csi24coi ，它們不僅提供了電源和微控制器的監控功能、不揮發性的數據存儲區、實時時鐘，而且其護c總線結構簡化了電路設計。
  11. System clock provides several synchronism clocks for every sub - circuit. reset circuit assumes that digital circuits have an initial state and self start

    系統時鐘電路分出多個同步頻率，以提供不同數字子電路的同步時鐘。
  12. The design of this asic ( application specific integrated circuit ) is more advanced in power consumption, clock & calendar circuit and reset circuit making it more competitive than similar domestic products

    該驅動電路asic的設計在功耗、時鐘日歷電路、復位電路等方面較國內同類產品有明顯改進，使得該晶元在市場競爭上將具有較大優勢。
  13. Remember to reset the clock

    記得把鬧鐘撥回去
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