data path delay 中文意思是什麼
data path delay
解釋
數據通路延遲-
After analyzing and comparing different partition rules, md32 pipeline architecture is finally defined, which meets the required instruction function, frequency and timing spec of md32. a complete set of creative design method for risc / dsp md32 micro - architecture is presented, such as parallel design, internal pipeline, central control, etc. thanks to the adoption of these design methodology, control path and data path are separated, circuit delay is reduced, and complex instruction operations are balanced among multiple pipeline stages
它們將若干復雜指令操作均勻分配在幾個流水節拍內完成，實現了任意窗口尋址等復雜指令操作，將整個處理器的數據通路與控制通路分離，減小了電路時延，從而滿足了risc dsp不同指令功能和系統時鐘頻率的要求，構成了統一的、緊密聯系的、協調的md32系統結構。 -
In the protocol, a hierarchy is currently used to manage the peers in the system, and a multicast path, which adapts to the request of delay and bandwidth, is constructed for the data transfer of media streaming
協議中利用分層拓撲結構來組織和管理應用層組播網路中的節點，在此基礎上構建滿足流媒體數據傳輸對延遲、帶寬要求的組播路徑。 -
After analyzing a common used ant colony routing algorithm, this thesis proposed a new fast adaptive routing algorithm to overcome the drawbacks of the ant - based algorithm. the new algorithm uses network delay information directly to choose path by probability. its application will minimize the delay for an end - to - end data transmission and optimize the distribution of network resources to avoid network congestion
演算法能夠憑借路徑時延信息並結合網路中各路徑的利用率情況自適應的調整發送路徑，並以概率的形式選擇路徑，一方面盡可能地使端到端數據傳送過程時延最小化，另一方面使網路流量分佈均勻，以減少網路擁塞發生的概率。 -
Warning : circuit may not operate. detected 4 non - operational path ( s ) clocked by clock clk with clock skew larger than data delay. see compilation report for details
這個問題好象比較嚴重，幫我看看，你遇到過沒有，他說不能正常工作了？
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