delay counter 中文意思是什麼

delay counter 解釋
延遲計數器
  • delay : vt 延遲,拖延,耽擱。 We ll delay the party for two week 我們要把會期延遲兩周。 The train was del...
  • counter : n 1 計算者;計算器;計數器。2 籌碼,號碼;偽幣;劣幣;〈蔑稱〉錢;棋子;湊數的人,玩具似的人。3 ...
  1. We implement the traffic generator by these studies. the thesis focuses on how to generate abundance flow, how to send flow fastly, how to measure network, how to synchronize flow sender and flow receiver. we use some solution to resolve the problems, including that using linear congruential and modifying select - giveup algorithm to generate random number, implement class that has good application interface to user, making random number as packet ’ s inter - departure - time and packet size, which can provide flow base on special distribution, designing and implementing a method to active measure by our traffic generator, designing a accurately time counter and precision delay function, synchronizing flow sender and receiver by tgm message

    通過對現有技術的研究和改進,我們形成的解決方案如下:通過利用改進的線性同余演算法,以及對舍選法進行研究和改進,實現了一個具有良好應用介面的隨機變量生成器,利用其產生的隨機數作為發包的間隔或包的尺寸,以產生服從特定模式的流;利用傳輸的數據包設計並實現了網路的主動測量,為網路測量和流的發送設計了高精度的計時器,精確延時函數;利用自定義的tgm報文協調發送端和接收端的操作。
  2. 4. demonstrating the structure and design of the counter + delay - line module, by which the pulse waveforms with given pulse delay and pulse width delay can be generated

    4 .設計計數器+延遲線模塊的組成及方案,並據此實現根據觸發信號產生的具有一定脈沖延遲和脈沖寬度的脈沖波形數字信號。
  3. The technology of very low bit rate for hf ( high frequency ) communication means that, one technology of ecm ( electronic counter measures ) resistant communication is developed for low bit data message exchange in the time of battle which data communication is destroyed by electronic disturber. it is regarded by armies in the battle of information, because that it can overcome the very low snr ( signal noise ratio ), very high narrow - band interference and multipath with maxium delay of fifty millisecond

    短波最低限度通信技術是在戰時強電磁干擾情況下能實現保證最低限度的數據報通信的一種抗干擾通信技術。由於其能有效的克服極低信噪比、較強的窄帶干擾和幾十毫秒的多徑,在信息戰中受到各軍高度重視。
  4. After a series of functional and time delay simulations, the design proved to be feasible and effective. the application indicates that the scheme is reasonable and the pxi - bus counter module meets the requirements of the design

    本文對pxi計數器的各項功能進行了功能模擬和時序模擬,並對其進行了調試和測試,測試結果表明:模塊設計方案合理、各項功能與指標均滿足設計要求。
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