frequency detector 中文意思是什麼
frequency detector
解釋
鑒頻器, 頻率檢波器-
The pll consists of a crystal oscillator, a ring voltage - control - oscillator, a frequency divider, a phase / frequency detector, a charge pump and a loop filter
設計的電路包括20mhz晶體振蕩器，鑒頻鑒相器，壓控振蕩器，固定分頻器，電荷泵和低通濾波器。 -
Superior frequency characteristics shortest recovery time, realize the switching of the circuit, complete functions such as open and close, clip wave, wave detector, high - frequency rectifier, logic control, which fit for all kinds of digital circuits and analog circuits
具有良好的高頻開關特性反向恢復時間短，可實現對電路開和關的控制功能，可完成開關限幅檢波高頻整流邏輯控制等功能，適用於各類數位電路類比電路。 -
Section ii describes the design approach and implementation of speech module on mcf5249 coldfire core. the speech codec optimizes g. 729a codes and added voice activity detection of g. 729b to save bandwidth ; the implementation of acoustic echo cancellation uses nlms algorithm and it can reduce echo though designing adaptive fir filter and speech detector ; the dtmf and cpt generate signal using two second order digital sinusoidal oscillators and detect signal by picking up the frequency information. but only get the frequency information is not enough in cpt detector, this thesis introduces a method
其中對語音編解碼器的設計採用優化g . 729a代碼達到設計要求，並在此基礎上加入g . 729b的靜音檢測模塊，以進一步降低網路傳輸帶寬;對回聲消除器的設計採用nlms演算法，通過設計自適應fir濾波器和語音檢測器達到回聲消除目的;對雙音多頻設計，信號發生端採用構造靜態參數表並通過二階正弦振蕩器產生信號，信號檢測端提取頻率信息以檢測信號;對呼叫進程音設計，除了類似雙音多頻的信號發生及頻率檢測設計外，還需要檢測信號持續時間，作者設計了一種基於匹配狀態表的方法以檢測信號持續時間。 -
Research on chaotic phenomena of phase - locked frequency detector with triangular phase - detector
三角形鑒相特性鎖相鑒頻器中混沌現象的研究 -
Research on the design of programmability frequency multiplier and phase detector on isp devices
器件的可編程倍頻鑒相邏輯電路的設計 -
Traditional delay estimation based on ica requires the trail sequences to initialize the receiver, but the new algorithm based on ica does not need the trail sequences. it is based on the channel character of downlink, using the ica algorithm to estimate the multi - path mixture matrix, then, find the delay information which is embodied by the column vector of the mixture matrix. the simulation results show that it does enhance the performance of traditional detector without wasting the invaluable frequency resource
傳統的通道估計演算法需要訓練序列使接收端的參數調整到理想狀態，而本文提出的基於ica的通道估計的多用戶檢測演算法不需要訓練序列，它是利用下行通道的固有特點，用ica的盲源分離法估計出多徑通道的卷積矩陣，從而從中提取出通道的延遲信息，模擬實驗結果證明這種方法在節省了頻譜資源的同時取得較好的估計效果，使得傳統的接收機的誤碼性能得到了很大的提高。 -
The present main product includes : has the wirelesshome use commercial security alarm system 、 has the wireless invasioninfrared microwave detector 、 the infrared correlation and theelectronic stockade border protection product 、 the smog fuel gasdetector 、 the security fitting ( gate magnetism 、 switch, button 、 warning light and so on ) 、 the infrared camera, a body camera 、 thenetwork camera 、 the network video frequency server 、 the hard diskvideorecorder and so on peacefully guards against the product
目前的主要產品有：有無線家用商用防盜報警系統、有無線入侵紅外微波探測器、紅外對射及電子柵欄周界防護產品、煙霧燃氣探測器、防盜配件（門磁、開關、按鈕、警燈等） 、紅外攝像機、一體攝像機、網路攝像機、網路視頻服務器、硬盤錄像機等安防產品。 -
Balanced frequency modulation detector
平衡調頻檢波器 -
The motive of this mm frequency synthesizer is also given in this chapter. chapter 2 emphasizes on the pll, first, introduce the module of basic components of pll, such as phase detector, loop filter and the voltage control oscillate ( vco ). secondly, describe the theory of the linearity pll
第一章介紹了頻率綜合器（簡稱頻綜）的發展過程，對各種頻率合成的技術進行了簡單的概括和對比，簡述了毫米波及其特點，並介紹了本文所作研究工作的研究目的及意義 -
The signal generator of sweep frequency is based on dds device ad9954, the signal measuring circuit is based on gain and phase detector ad8302, the real - time control and deal circuit is based on tms320vc5409, and the periphery interface circuit is based on at89s52. the system can generate sweep frequency signal with the frequency range from 100khz to 150mhz, and with the power range from - 45dbm to + 18dbm. it can measure the gain and phase of the network, display the measure data by liquid crystal displayed and print it by the printer
該測試儀以dds晶元ad9954為核心構成掃頻信號源電路，以增益相位檢測器ad8302為核心構成檢測電路，以dsp晶元tms320vc5409為核心構成控制與運算電路，以及以at89s52為核心構成外圍介面電路。該測試儀能產生頻率范圍達100k ~ 100mhz ，功率范圍為- 45dbm ~ + 18dbm的掃頻信號，能對被測網路的頻率特性進行測量，並留有豐富的外圍介面，可以將測量數據繪圖通過lcd顯示或者由印表機列印輸出。 -
In the paper, the design of the real - time test system for crystal parameters is presented. the signal generator of sweep frequency based on dds device ad9852, the signal measuring circuit based on gain and phase detector ad8302, and the real - time control and deal circuit based on tms320vc5416 and the design of high - speed printed digital & analog circuit board are discussed in details
本文闡述了晶振實時測量系統的設計，介紹了以dds晶元ad9852為核心的掃頻信號源電路，以增益相位檢測器ad8302為核心的信號檢測電路，以dsp晶元tms320vc5416為核心的實時控制與運算電路，以及高速數模混合電路板的設計方法。 -
In this method, the phase difference between two compared signals that have same nominal frequency can be converted into voltage signal by phase detector. the voltage signal varies linearly with the phase difference and can be displayed or recorded by some instruments
此方法是將兩個被比對的標稱值相同的標準頻率信號之間的相位關系，通過線性鑒相器轉換成與它成線性關系的電壓信號，並通過相應的設備進行顯示紀錄。 -
The basic operation principle of phase - locked frequency synthesizer and the type of circuits are expatiated systematicly in this paper. the principle of operation on sampling phase detector and some characteristics including the linear tracking and phase noise in phase loop circuits are analyzed deeply. the research is emphased on the theory and design method of circuits in the sampling phase - locked frequency synthesizer. then, the expansion capturing circuit is analyzed and designed for better performance of capturing loop circuits. at last, the loop filter is also analyzed and contrived taking account of effection of additional phase shift by the sampling - holder. the general research on the theory and technology of sampling phase lock in the paper will make a basement for the development of new product
本文系統的闡述了鎖相頻率合成器的基本工作原理及電路類型；較深入地分析了取樣鑒相工作原理及電路、鎖相環路的線性跟蹤特性和相位噪聲特性；重點對取樣鎖相頻率合成器電路理論和設計方法進行了研究；為了改善環路的捕獲性能，對擴捕電路進行了分析和設計，並用wewb32軟體對電路進行了模擬；考慮到取樣保持器的附加相移影響，對環路濾波器進行了分析和設計。 -
In the design, the diode of agilent ' s hsch - 9161 is used. with the diode circuits in parallel, the millimeter - wave short pulse detector has been designed. it works at the frequency of 37 to 38ghz, and the pulse duration is 400ps
本文採用agilent公司的hsch - 9161檢波二級管，選取二極體並聯檢波電路形式，完成了工作頻率為37 ~ 38ghz 、脈沖寬度為400ps的毫米波短脈沖檢波器的研製，同時設計了一個毫米波短脈沖調制器。 -
Then according to the emphasis of the design, went deeply into the theory of pll frequency synthesizers widely used, described pll ’ s working principle, structure and several types in detail, and made research and analysis of pll frequency synthesizers ’ phase noise, including the effect of the active loop filter on the phase noise, and give some methods to make improvement as well, such as changing loop filter form, reducing divide number, and increase phase detector frequency, etc. then paper introduced the principle character and phase noise analysis of direct digital frequency synthesizer ( dds ) and injection phase lock circuit, which are also important circuits in the design
論文首先對幾十年頻率合成器的發展進行概述，而後針對本次設計的重點，對應用較為廣泛的鎖相頻率合成理論進行了深入的探討，詳細介紹了鎖相環的工作原理、組成結構和鎖相類型，並對鎖相頻率合成器的相噪特性進行了研究分析，包括有源環路濾波器對于相噪的影響，提出了改善相位噪聲的幾點措施:改善環路形式、降低分頻數、增大鑒相頻率等。接著介紹了直接數字頻率合成器（ dds ）和注入鎖相電路的原理特點以及相噪分析，它們也是本次設計的重要電路。 -
The thesis describes a prototype fractional frequency synthesizer which is supported by a project granted by the ministry of science and technology of pr china. firstly, based on the principle of pll, this paper briefly describes three basic pll components : phase detector ( pd ), low pass filter ( lpf ), voltage controlled oscillators ( vco ), analyzes the linearized pll and summaries the transfer functions of third - order pll with ideal intergrator filter respectively. based on a microwave vco, the single point frequency pll frequency ranging from 2. 2 to 2. 5ghz is developed
首先，從鎖相環的基本理論、原理出發，分析了鎖相環中的三個基本部件：鑒相器、環路濾波器和壓控振蕩器，此後，針對線性化鎖相環進行了分析，研究了在使用比例積分濾波器時，三階鎖相環的環路參數計算；在電路實現時選用了lmx2353 ，在此基礎上，完成了2 . 2 ~ 2 . 5ghz范圍內的小數頻率合成器設計。 -
The peripheral controller consists of frequency detector, data sample controller, fifo, lcd driver and the interface circuit between dsp and fpga
外圍控制器囊括了硬體系統中幾乎所有的數字電路，包括頻率/周期測量、數據採集控制、 fifo 、 lcd驅動以及fpga與dsp之間的介面電路等。 -
Simplified version of frequency detector derived from the maximum - likelihood principle
基於最大似然原理的低復雜度頻率檢測器 -
The main contribution of the thesis is seen as follows : aiming at the fault with slow speed and high power dissipation of the conventional phase - frequency detector, a high speed and low power dissipation phase - frequency detector is designed by modifying the structure of the single phase lock dynamic d flip - flop and adding the delay cell in the feedback loop to eliminate the phase detector ’ s dead zone effectively
論文的主要貢獻為以下幾個方面: 1 .針對傳統鑒頻鑒相器速度慢、功耗高的缺點，改進了單相時鐘動態d觸發器的結構，設計出了一種高速低功耗的鑒頻鑒相器，在反饋迴路上加入延遲單元，能有效的消除鑒相死區。 -
But its performance is as same as common pll at a 5v voltage. so the pll performance is better than other plls at a 5v voltage, especially in power consumption and frequency. finally, the improved pll circuit used in the frequency synthesizer is composed of the improved vco, phase / frequency detector and charge pump. hspice simulation results show that the pll performance is better than other plls implemented by other vco in the same cmos technology
綜合以上的研究與設計，本文用所改進的壓控振蕩器、無死區鑒相器及電荷泵電路組成了用於頻率合成的鎖相環電路，並對此電路進行整體設計及模擬，結果表明其在鎖定時間、頻率范圍、輸出相位抖動及功耗方面具有較好的性能，且對提高鎖相環頻率合成器的整體性能有一定的作用。
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