gate level simulation 中文意思是什麼
gate level simulation
解釋
門電路級模擬- gate : n 1 大門，扉，籬笆門，門扇。2 閘門；城門；洞門；隘口，峽道。3 【冶金】澆注道，澆口，切口；【無線...
- level : n 1 水平儀，水準儀；水準測量。2 水平線，水平面；水平狀態；平面，平地。3 水平，水準；水位；標準；...
- simulation : n. 假裝；模擬；裝病，裝瘋；【生物學】擬態，擬色。
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After that, the system and function simulation platform are introduced, and the simulation results are analysed. moreover the gate - level simulation is done after the ip code is synthesized
之後，介紹了此ip核的系統模擬平臺和功能模擬平臺，並對端點0的各個邏輯功能塊的功能模擬的結果進行了分析。 -
Speed - up techniques for gate - level power estimation are proposed. an efficient power estimation flow is presented firstly to reduce the power simulation time
本文的主要貢獻如下: 1 .提出了加速門級功耗模擬與分析的方法。 -
It presents the verification strategy used in the whole eda design flow of the chip. the simulation on module level ( inc. post - layout ) uses the software event - driven simulator, the simulation of the associated modules or whole system uses cycle - based simulator and hardware emulator, for the gate - level netlist produced by using top - down design flow, the sta tool can analyze the static timing, and more formal verification is used to ensure the correct function
本章還提出了系統在整個eda設計流程中的設計驗證策略方法：模塊級的模擬（包括布線后的模擬）全部採用事件驅動式的軟體模擬工具來驗證，各大模塊的聯合模擬及整個晶元的功能驗證（寄存器傳輸級與門級）使用基於周期的模擬工具和硬體模擬器；對于採用top - down的設計方法得到的門級網表使用專門的靜態時序分析工具來進行時序分析以及採用形式驗證來保證正確的功能。 -
The test bench program is a virtual pci system, which comprise the microblaze model established from xilinx edk and also the pci / pci - x model from synopsys company. function level or gate level simulation can be done on this test bench
測試平臺中，利用xilinxedk生成的microbalze處理器模擬模型，以及synopsyspci / pci - xflexmodels模型組建了一個虛擬的pci系統，可進行門級和行為級的模擬。 -
The design of mcs - 51 microcontroller is followed the top - down design way, including system partition coding ( vhdl ) rtl simulation synthesis, gate level simulation ect
對mcs ? 51單片機進行正向設計，包括系統劃分、編寫代碼、 rtl級模擬與綜合、門級模擬等。 -
And the process of functional verification consists of the implementation of rtl ( register transfer level ) simulation, gate level simulation and post - layout simulation in the process of design
驗證最關鍵的是測試方案的制定，而功能驗證的過程是在於在設計過程中實施rtl級模擬、門級模擬和后模擬。
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