gating the clock 中文意思是什麼
gating the clock
解釋
選通時鐘-
In this paper, low power flip - flops designs by the reduction of the load of clock or the data path ; by the reduction of clock swing ; by the reduction of clock frequency and by the reduction of those idle transitions in cmos circuits with clock gating are discussed
與此相對應的，在本論文中，分別對將少時鐘負載或數據通路的負載的觸發器設計；減小時鐘信號幅度的觸發器設計；降低時鐘頻率的雙邊沿觸發器設計以及應用門控技術來減少觸發器無效跳變設計的觸發器結構進行了討論。 -
In fact, it is more effective in system level. low power technique of microprocessor is composed of clock - gating, close part of cache, and dvs ( dynamic voltage scaling ). low power technique of peripheral equipments design is composed of closing the idle parts of the equipment and degrading the service quality satisfied with lowest requirement
處理器的低功耗設計大都採用系統級，其技術主要包括:門控時鐘技術， cache部分關閉技術，動態電壓縮放dvs （ dynamicvoltagescaling ）技術;外圍設備低功耗設計包括:關閉設備空閑部件;在滿足基本性能要求前提下，降低外圍設備的服務質量。 -
To avoid the idleness state and the corresponding power dissipation in sequential circuits, a clock gating technique and a multi - code assignment using redundant state is adanced to reduce power dissipation
為抑制時序電路中的冗餘現象，研究了時序電路的門控時鐘技術，並利用t型觸發器進行時序電路設計。
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