hierarchical decoding stage 中文意思是什麼
hierarchical decoding stage
解釋
層次譯碼階段- hierarchical : adj. 1. 僧侶統治（集團）的。2. 統治集團的。3. 等級（制度）的。adv. -cally
- decoding : 解解碼
- stage : n 1 講臺；舞臺；戲院，劇場；〈the stage〉戲劇，戲劇藝術；戲劇文學；〈the stage〉戲劇業；劇壇。2 ...
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Then, memory cell array and some parts of peripheral circuits used in sram, for example, sense amplifyier and adderss decoder, are designed and verifyied by simulation. furthermore, some novel methods, such as clocked hierarchical word decoding structure, multi - stage sense amplifyier, common data line and data bus equlibruim technology has been applied in the design of 128kbit and imbit sram. what ' s more, we have studied compiler technology applied in the designing course of a imbit full cmos sram from the pointview of methology
然後對sram的存儲單元電路以及外圍電路中的靈敏放大器和地址譯碼器進行了設計和模擬，在此基礎上，以128kb和1mb全cmossram設計為例，從方法學角度對同步sram設計中的帶時鐘分等級字線譯碼，多級靈敏放大和位線及總線平衡等技術進行了研究，並給出了相應的compiler演算法。 -
Hierarchical decoding stage
層次譯碼階段
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