input clock 中文意思是什麼
input clock
解釋
輸入時鐘-
The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing
本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。 -
The level adjustment circuit 100 lowers the clock signal input to the first clock terminal ck1 by a predetermined value from h level and provides the signal to the gate of the transistor q5
電平調節電路100將送往第一個時鐘終端ck1的時鐘信號從h電平降低一個預定值，並將此信號送往晶體管q5的輸入端。 -
This logic is designed containing input signal delay, event type classification, event pre - scaling and timing logic and works in pipeline mode under control of 20mhz clock which ensures no dead time contribution
主觸發邏輯在20m時鐘下以流水線的方式工作，保證沒有死時間的產生。第二個例子是任意數字信號發生器的設計。 -
The concept of " timing " in the article is not the clock in our ordinary living, but syntheses which is made up of some frequency source in the signal generator ( such as cs atom frequency standard, rb clock & high accuracy quartz crystal oscillator ) which produces the primary frequency, the matching input interface and the matching output interface and controlling circuit etc. for example, bits is a kind of timing equipment, which is used to control the timing of some functions
本文論及的「時鐘」概念不是指日常生活中使用的鐘表，而是由產生基準頻率的信號發生器（如銫原子頻率標準、銣鐘及高精度石英晶體振蕩器等）中的某種頻率源以及相配套的輸入、輸出介面和控制電路等組成的一整套具有特定同步定時功能的綜合體。如bits就是一種時鐘設備，它提供用在通信系統中控制某些功能的定時的時間基準設備，時鐘提供的信號稱為基準信號、定時信號或同步信號。 -
The host computer system ' s functions are as follows : duplex communicate with automatic station data poll gather to each automatic station save and handle the data format and print diagram based on the gathered data download the parameter to automatic station and adjust the clock dial - up to network and long - distance control automatic rainfall station consists of outer garment, meet rain bucket, water input and output electromagnetic valve, measure bucket, storage battery and circuit control
可以與自動站進行雙向通訊，完成對各個自動站數據輪詢採集並進行存儲、處理，並生成圖表，根據採集的數據形成圖表、列印，可以向自動雨量下載參數、時鐘校準以及遠程聯網撥號和控制。自動雨量站包括外罩、接雨桶、進放水電磁閥、測量桶、蓄電池以及電控部分等部分組成。 -
Continuing, this paper has detailedly presented all writer have achieved works, which involve designing and implementing audio data assignment func tion, software on - line upgrade function, real time clock driver programme, user input process function, and testing the terminal ' s interoperability with some other h. 323 devices
接著，介紹了作者完成的工作：設計實現了語音數據調度功能、軟體自更新功能、實時時鐘驅動程序和用戶輸入處理功能，以及終端與其它相關的h 323設備的互通測試。 -
Based on the system clock and trigger input signals, using fpga to generate trigger output signals in given working modes
3 .通過fpga實現在一定系統時鐘和觸發信號作用下各種工作模式的觸發信號的產生。 -
That is, during clock Ф2 with the aid of clock Ф1, the logical information of the input is stored into the memory element.
這就是說，在時鐘2期間，在時鐘1的作用下，使輸入的邏輯信息存入存貯元件中。 -
According to different function, the hardware part is divided into processor module, analog signals input and converting module, digital signals module, communication module, clock module and display module
按照功能的不同，硬體劃分成處理器系統模塊、模擬信號輸入和轉換模塊、開關量輸入輸出模塊、通信模塊、時鐘模塊、鍵盤顯示模塊、電源模塊。 -
Input to the inverting oscillator amplifier and input to the internal clock operating circuit
反向振蕩放大器和內部時鐘工作電路的輸入。 -
This module works with a clock of 40mhz and its input accept lvds signal, output are both in lvds and ecl standard. the setting of the delay parameters is realized with vme software commands
該插件的工作由40mhz時鐘控制，輸入電平為lvds 、輸出為lvds和ecl電平，其初始化通過vme總線加載，並具有多種編程下載方式。 -
An improved high - resolution current - mode sorter is presented. its structure complexity is o ( n ), which is crucial to the expansion of its size, and its dynamic range is large. only one clock signal and one reset signal are needed. no biasing signal is required. the operation point is constructed according to the input current, so it is self - adaptive, which is very important for an all - purpose component. in average value circuit, subtraction circuit, winner - take - all ( wta ) circuit and control circuit, it has good performance even at a large input current. this sorter has high precision, high resolution and low power, as has been proved via hspice simulation. it can be implemented in the standard digital cmos technology and widely used in many fields, so it is of great value in applications
提出了一種改進的高精度電流型排序電路.它的結構復雜性僅為o （ n ） ，便於擴展;動態范圍大;它是自適應的，工作點由輸入電流確定，故不需要偏置信號，這對作為通用器件使用的排序電路來說是很重要的.通過利用平均值電路、減法電路、 wta電路和控制電路，可以使該電路在大輸入電流下依然保持高性能. hspice模擬表明該電路具有高準確性、高精度、低功耗的特點.它能用標準數字cmos工藝來實現，可以被應用於很多領域，具有很高的應用價值 -
The periphery electric circuit of adc was designed, including 3 - wire serial port configuration circuit, analog input electric circuit, clock input circuit and power
對adc的外圍電路進行設計，包括三線串口配置電路、模擬輸入電路、時鐘輸入電路和電源電路。 -
In order to improve reliability and simplify the hardware design, many new i2c bus elements were used to realize binary input, logic output, clock functions and storing settings and reports. by simulating i2c bus data transfer, the mcu realized writing and reading data from each element the whole hardware system ' s structure is compact and reasonable, and the device has high reliability, stability and immunity to disturbance
從提高可靠性和簡化電路的角度出發，設計硬體電路板時使用了許多新型i ~ 2c串列介面器件， mcu用普通i / o口模擬i ~ 2c總線介面，由軟體模擬i ~ 2c總線數據傳輸過程，實現了開入開出、定值存儲、報告存儲和時鐘對時等功能。 -
Software design includes many aspects, such as design of interface, interrupt and clock control, monitoring, etc. sampling and accessing quickly data of chromatogram peak is an important tache to ensure analytic and real time performance of chromatograph, fifo make high - speed input and output of a / d sampling data possible, and expended memory, instead of disk, save a great deal of peak data and process parameter
硬體系統由cpu 、 a / d 、 d / a 、顯示驅動、實時鐘五個模塊組成，軟體設計包括譜峰數據的高速採集和存取、人機界面的設計、中斷和實時鐘控制、監測控制等方面的工作。譜峰數據的高速採集和快速存取是保證工業色譜儀分析性能和實時性的重要環節，採用了fifo存儲器技術實現a / d采樣數據的高速輸入輸出，使用擴展內存代替硬盤存貯過程參數和海量的譜峰數據。 -
The third, according to the aforementioned project, a hardware system is provided which includes the core chip - tms320dsc21 ( ti special dsp ) and its peripheral circuits ( clock and power supply ), video input module, network output module, alarm module, and cradle head control module. the design and debug of hardware system is finished
接著以ti公司的專用dsptms320dsc21為核心，進行了嵌入式網路攝像機的硬體設計，硬體部分包括： dsc21核心及相關電路（時鐘、電源和調試電路） 、視頻輸入模塊、視頻數據網路輸出模塊、報警模塊和雲臺控制模塊。 -
Especially it allows various types of interruptions of external digital input, timer output and a / d conversion, each type of interruption has its own role in the signal measurement or in exact pace control, its fifo buffer function makes it possible to work at the sampling rate of 200k samples per second without carrying over - burden interruption rate, its latch type external interrupt request along with its high frequency clock makes a precise locating of pulse edges possible
該控制系統在工作過程中，有多種產生於不同部件的信號需要檢測，其中有模擬輸入信號十三路，數字輸入信號三路，通過數據採集和信號分析，判斷該控制系統工作是否正常。結合系統檢測的具體要求，本論文從硬體設計和軟體設計兩個方面，實現了數據採集系統的硬體介面電路和軟體演算法。 -
The effects of sampling clock jitter on signal - to - noise ratio ( snr ) and effective bit ( enob ) performance discussed in section 3 are even more dramatic in undersampling applications because of the higher input signal frequencies
在第三章討論的采樣時鐘抖動對信噪比和有效位性能的影響在欠采樣應用中因為更高的輸入信號頻率顯得更有戲劇性。 -
Operates from a wide range of input clock frequencies
輸入時鐘的頻率寬范圍 -
Analyzing every part ’ s function and characteristic, i improve overflow control unit ’ s design technique to suit fpga design and traditional register exchange survivor managing algorithm. the system use input clock as system clock and use parallel structure in system to provide flexible speed
採用適合fpga特點的溢出控制設計方法;改進傳統的寄存器交換法re （ registerexchange ）的倖存路徑管理設計方法;全系統採用輸入數據的同步時鐘作為系統時鐘，系統內部採用全并行的方式，以提供靈活的速度。
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