interrupt bus 中文意思是什麼
interrupt bus
解釋
中斷總線-
During the design of vxi - bus serial controller module, the functions of vxi - bus including time - sequence for vxi interface, resource management, interrupt process, bus arbitration, are accomplished. to advance the performance and stability, the fpga technic is used to implement the kerneled code including serial bus time - sequence switching to vxi interface time - sequence, the uart, the parameterized baud generator and “ pipeling frame ”. the handle type of data transfer bus for vxi - bus is researched thoroughly, and the format of serial data transfer is designed
在vxi總線串列控制器設計中，實現了vxi總線控制器的基本功能，包括vxi總線介面時序、總線仲裁、超時處理等;同時利用先進的fpga技術實現了串列總線時序向vxi總線時序的轉換、通用異步收發器（ uart ） 、參數化波特率發生器、流水線結構等功能模塊;在設計中還深入研究了vxi總線數據傳輸的各種操作類型，制定了串列數據傳輸的編碼格式。 -
System is made up of two parts of hardware and software, hardware part include ecg signal receive, enlarge and filter circuit and gather circuit two parts among them, design isa and pci two bus collection card of form separately ; software part include and can programme and run side by side 8255 interface and cpld and interface software design of ad574a, using interrupt way to design the software of data collecting, and realization of data compress, and software design of administrative system
本系統由硬體和軟體兩部分組成，其中硬體部分包括心電信號的接收、放大和濾波電路以及採集電路兩部分，分別設計了isa和pci兩種總線形式的採集卡；軟體部分包括可編程并行介面8255和cpld與ad574a的介面軟體設計、中斷方式數據採集系統的軟體設計、數據壓縮以及病例管理系統的軟體設計。 -
The down - up design includes the researches of decoder schematics, controller schematics, pipeline schematics, bus schematics, stack schematics and interrupt schematics. the thesis content and outcome of research are beneficial to the design of a cpu design project. at the same time, these contents are beneficial to the design of a microcontroller
整個正向設計由於採用了簡化的措施，還存在一些不足，因此從逆向設計的角度，研究了pic微控制器晶元中處理器的電路實現結構，主要包括譯碼電路和控制器電路的實現結構，流水線電路的實現結構，處理器內總線的實現結構，以及堆棧和中斷電路這些與處理器電路有密切相關性的子電路單元。 -
3. realize the interface between pci9054 and the pci bus, including the bus arbitration, read and write of the registers, the configuration of the eeprom, the dma transfer, interrupt response and so on
3 .實現pci9054與計算機pci總線的介面，包括總線仲裁，寄存器讀寫操作， eeprom的配置和下載， dma傳輸，中斷響應等功能。 -
The peripheral equipment, which includes serial control, b3g test tools, ddr control, interrupt control, connect the on - chip peripheral bus of powerpc ~ ( tm ) 405. in addition, the clock module and the misc logic module are necessarily to make the b3g test platform work. in order to debug the b3g test platform, the chipscope ~ ( tm ) core is adopted
在powerpc ~ （ tm ） 405的外圍總線上開發了串口控制器、 b3g測試工具、雙倍數據流（ ddr ）內存控制器、中斷控制器等外設;整個系統還需要時鐘、輔助邏輯等模塊;為了方便b3g測試平臺的調試，將chipscope ~ （ tm ）核也嵌入到了平臺中。 -
Can ( controller area network ) is famous for its excellent real - time ability and high performance to cost ratio. can is a typical event - triggered field - bus, and can applications exhibit low bandwidth utilization ratio. a time - triggered scheduling method for the can 2. 0 has been presented by use of hardware periodical interrupt of micro - controller and software programming technique
（ 2 ） can （ controllerareanetwork ）總線技術實時性好，性價比高，但這種事件觸發型現場總線網路利用率較低，針對can總線在分散式系統中的應用，利用微控制器的硬體定時器，結合軟體編程，提出了一種can總線的時間觸發調度方法。
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