jtag 中文意思是什麼

jtag 解釋
成邏輯可通過編程配置電路
  1. In the logic design, the fundamentals and characteristics of ieee std. 1149. 1 specification and usb protocol are introduced first of all. according to altera ’ s fpga cyclone, it analyzes the architecture and jtag instructions of boundary scan test ( bst ). then the dissertation analyzes how to program cyclone device and offer the scheme of the design which is realized in verilog hdl by modelsim and quartus ii software

    在介面邏輯設計中，首先分析ieee1149 . 1標準和usb協議，理解邊界掃描測試和usb數據傳輸的工作方式，然後針對altera公司的fpga器件cyclone ，通過分析它的邊界掃描測試結構和各種jtag指令，研究它的編程過程和編程特點，並提出設計方案。
  2. Throughout this article and accesses the flash chip of the target using the parallel port through the jtag interface

    ）上執行並通過jtag介面使用并行埠訪問目標的閃存晶元。
  3. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  4. In the hardware, the conversion from serial port, parallel port or usb port to jtag port is realized by a cpld component, by which the volume of the emulator can be reduced and its reliability can be enhanced as well. the feature of this paper is the design of software section

    硬體部分主要採用了cpld器件來實現串口，並口， usb口到jtag口的邏輯轉換，採用cpld器件來實現此轉換功能不但減小了模擬器的體積，而且還增強了模擬器的可靠性。
  5. The hardware circuit is designed for the system, including the power module, clock circuit module and jtag interface

    對整個系統的硬體電路進行了設計，包括相應的電源模塊、時鐘電路模塊、電平轉換模塊和jtag介面。
  6. The hardware system includes power supply circuit, clock reset circuit, jtag model building circuit, decoding circuit, memory interface circuit, man - machine interface circuit and numeric control constant - current source interface circuit

    硬體系統主要包括電源電路、時鐘復位電路、 jtag模擬介面電路，譯碼電路、存儲器介面電路、人機介面電路、 adc轉換電路和數控恆流源介面等。
  7. The test system including power circuit, restoration circuit, pulse circuit, the circuit of the memory ( sram and flash ), jtag interface circuit, the control circuit of the touch - panel, lcd interface circuit

    該測試系統的功能模塊包括電源電路，復位電路，晶振電路，存儲器電路（ sram和flash ） ， jtag介面電路，觸摸屏控制電路， lcd介面電路。
  8. Board - level design for testability based on jtag

    的板級可測試性設計
  9. At last, the bit file is downloaded into the device through jtag interface and the function of the device is verified by online logic analyzer chipsocpe

    最後，將位流文件通過jtag介面下載到晶元中。並使用在線邏輯分析儀chipscope對下載后的器件的功能進行了在線驗證。
  10. The content of fpga is downloadable via prom, jtag or the special port on chip by xilinx software. the module can delay input signals from 0ns to 1. 8us stepping by 25ns. it ' s precision is 25ns

    插件經過測試，能在0 71時鐘周期之間，以一個時鐘周期為步長實現對輸入信號的可編程延遲，延遲精度為25ns ，滿足觸發判選系統總觸發邏輯對齊來自各個探測器觸發子系統信號的要求。
  11. In the part of the hardware, how to select chips is introduced, including dsp and other chips, such as power supply 、 sdram 、 flash and jtag which is a emulator interface ; in addition, the clock 、 assignment to memory and the table of vectors are set

    其中在硬體部分，介紹了晶元的選擇方法，包括dsp晶元和其它晶元，如電源晶元、異步動態存儲器、閃存和jtag模擬介面;還對硬體平臺的時鐘、內存分配和中斷向量表進行了設置。
  12. It was used jtag interface to download the program to the flash memory of c8051f020

    並把程序用jtag介面下載到c8051f020的flash存儲器中。
  13. This software uses the jtag port on the target in embedded development, the embedded device is often referred to as the

    這個軟體使用目標（在嵌入式開發中，嵌入式設備通常被稱為
  14. Here the jtag ? is used to connect the emulator and micro - chip. there are two sections of the emulator : hardware and software

    作者研製的c8051fxxx系列單片機模擬器通過jtag口對單片機進行模擬，模擬器主要分為兩部分，硬體部分和軟體部分。
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